Semiconductor devices, assemblies, and associated methods
A semiconductor device assembly can include an assembly substrate having a top surface with a die stack thereat. The die stack can include a first and a second die, and each dies can include a die substrate with a top and a bottom surface. The top surface can include a first region a first distance from the bottom surface, and a second region a second distance, greater than the first distance, from the bottom surface and with a bond pad thereat. The bottom surface of the first die can bond with the top surface of the assembly substrate, and the bottom surface of the second die can bond with the first region of the first die top surface. In some embodiments, the assembly can further include additional die stacks and/or additional dies within one or more die stacks.
1 . A semiconductor device assembly, comprising:
an assembly substrate including a top surface; and
a die stack at the top surface including a first die and a second die, each of the first and the second dies having:
a die substrate having a planar bottom surface and a top surface;
a first region of the top surface a first distance from a first plane in which the planar bottom surface lies;
a second region of the top surface a second distance, greater than the first distance, from the first plane in which the planar bottom surface lies;
a bond pad at the second region of the top surface;
an active component formed in the die substrate beneath a second plane in which the first region of the top surface; and
a conductive structure extending from and directly electrically connecting the bond pad to the active component,
wherein the die substrate includes an RDL above a plane of the first region and below a plane of the second region, and wherein the RDL includes the bond pad and at least a portion of the conductive structure;
wherein the planar bottom surface of the first die is bonded to the top surface of the assembly substrate and the planar bottom surface of the second die is bonded to the first region of the top surface of the first die.
2 . The semiconductor device assembly of claim 1 further comprising a third die and a fourth die, each of the third and fourth dies having:
a die substrate having a bottom surface and a top surface;
a first region of the top surface a first distance from the bottom surface;
a second region of the top surface a second distance, greater than the first distance, from the bottom surface; and
a bond pad at the second region of the top surface;
wherein the bottom surface of the third die is bonded to the top surface of the assembly substrate spaced from the first die, and the bottom surface of the second die is bonded to the first region of the top surface of the first die.
3 . The semiconductor device assembly of claim 1 further comprising a third die and a fourth die, wherein the bottom surface of the third die is bonded to the first region of the top surface of the second die, and wherein the bottom surface of the fourth die is bonded to the first region of the top surface of the third die.
4 . The semiconductor device assembly of claim 1 further comprising a wire segment, wherein the wire segment is coupled between the bond pad of the first die, the bond pad of the second die, and the assembly substrate.
5 . The semiconductor device assembly of claim 1 , wherein the first die and the second die each include the second region of the top surface along a peripheral side edge of the first and the second die, respectively.
6 . The semiconductor device assembly of claim 5 , wherein the second region of the top surface of the first and the second dies are laterally adjacent.
7 . The semiconductor device assembly of claim 1 , wherein the first and the second dies are shingled relative to one another.
8 . The semiconductor device assembly of claim 1 , wherein the first and the second dies are encased in a mold material.
9 . A semiconductor die, comprising:
a die substrate including a planar bottom surface and a top surface;
a first region of the top surface a first distance from a first plane in which the planar bottom surface lies;
a second region of the top surface, adjacent to the first region, a second distance greater than the first distance from the first plane in which the planar bottom surface lies;
a bond pad at the second region of the top surface;
an active component formed in the die substrate beneath a second plane in which the first region of the top surface; and
a conductive structure extending from and directly electrically connecting the bond pad to the active component,
wherein the die substrate includes an RDL above a plane of the first region and below a plane of the second region, and wherein the RDL includes the bond pad and at least a portion of the conductive structure.
10 . The semiconductor die of claim 9 further comprising a third region between the first and the second regions, and extending from the first region to the second region.
11 . The semiconductor die of claim 9 , wherein the die substrate excludes any portion of an active component above a plane of the first region and below a plane of the second region.
12 . The semiconductor die of claim 9 , wherein the second region extends along a first side edge of the die substrate.
13 . The semiconductor die of claim 12 , wherein the second region further extends along a second side edge of the die substrate, the second side edge extending from a corner of the die substrate shared with the first side edge.
14 . The semiconductor die of claim 9 , wherein a difference between the first distance and the second distance is greater than 5 μm.
15 . The semiconductor die of claim 9 further comprising a plurality of bond pads at the second region of the top surface.
16 . The semiconductor die of claim 9 , wherein a difference between the first distance and the second distance is greater than the first distance.