Efficient clocking scheme for die-to-die connectivity
An integrated circuit (IC) chip includes a first data receiver including first receiver circuitry to receive first data from a second IC chip. A second data receiver includes second receiver circuitry to receive second data from the second IC chip. Timing circuitry couples to the first receiver and the second receiver in a shared configuration. The timing circuitry generates a receive timing signal to time reception of the first data and the second data by the first and second receivers. The timing circuitry generates the receive timing signal through use of a phase adjustment circuit. The first and second receivers sample the first and second data in response to the receive timing signal. The timing circuitry includes a forwarded timing interface for transferring a forwarded timing signal between the IC chip and the second IC chip.
1 . An integrated circuit (IC) chiplet, comprising:
a first number of multiple data receivers, each of the multiple data receivers comprising a clock input to receive a common clock signal;
wherein the first number of multiple data receivers are organized into subsets of data receivers, each subset of the subsets of data receivers comprising:
a second number of data receivers that is less than the first number of multiple data receivers, the second number of data receivers to receive data signals at substantially a same time; and
phase adjustment circuitry that is shared solely by the second number of data receivers, the phase adjustment circuitry to generate a sampling clock signal by adjusting a timing of the common clock signal to sample data signals of the subsets of data receivers.
2 . The IC chiplet of claim 1 , wherein:
the adjusting of the timing of the common clock signal is based on the timing of a data signal received by at least one of the second number of data receivers.
3 . The IC chiplet of claim 1 , wherein:
the common clock signal is generated by a common clock phase adjustment circuit and forwarded from a second IC chiplet.
4 . The IC chiplet of claim 3 , wherein:
the common clock phase adjustment circuit comprises a phase interpolator that adjusts the timing of the common clock signal by coarse phase increments of a first phase granularity.
5 . The IC chiplet of claim 4 , wherein:
the phase adjustment circuitry comprises a variable delay circuit that adjusts the timing of the common clock signal by fine phase increments of a second phase granularity that is finer than the first phase granularity.
6 . The IC chiplet of claim 1 , wherein:
the adjusting of the timing of the common clock signal based on the timing of a data signal received by at least one data receiver before being distributed to the subsets of the data receivers.
7 . The IC chiplet of claim 1 , wherein:
each subset of the subsets of data receivers comprises a pair of adjacent data receivers.
8 . A chiplet-based system-in-package (SiP), comprising:
a first integrated circuit (IC) chiplet comprising a first number of multiple transmitters to transmit multiple data signals;
a second IC chiplet coupled to the first IC chiplet via multiple data lanes, the second IC chiplet comprising
multiple data receivers coupled to the first number of multiple transmitters via the multiple data lanes, each of the multiple data receivers comprising a clock input to receive a common clock signal;
wherein multiple data receivers are organized into subsets of data receivers, each subset of the subsets of data receivers comprising:
a second number of data receivers that is less than the multiple data receivers, the second number of data receivers to receive data signals at substantially a same time; and
phase adjustment circuitry that is shared solely by the second number of data receivers, the phase adjustment circuitry to generate a sampling clock signal by adjusting a timing of the common clock signal to sample data signals of the subsets of data receivers.
9 . The chiplet-based SiP of claim 8 , wherein:
the adjusting of the timing of the common clock signal is based on the timing of a data signal received by at least one data receiver.
10 . The chiplet-based SiP of claim 8 , wherein:
the first IC chiplet comprises a common clock phase adjustment circuit to generate the common clock signal and to forward the common clock signal to the second IC chiplet.
11 . The chiplet-based SiP of claim 10 , wherein:
the common clock phase adjustment circuit comprises a phase interpolator to adjust the timing of the common clock signal by coarse phase increments of a first phase granularity.
12 . The chiplet-based SiP of claim 11 , wherein:
the phase adjustment circuitry comprises a variable delay circuit that adjusts the timing of the common clock signal by fine phase increments of a second phase granularity that is finer than the first phase granularity.
13 . The chiplet-based SiP of claim 8 , wherein:
the adjusting of the timing of the common clock signal is based on the timing of a data signal received by at least one of the second number of data receivers before being distributed to the subsets of the data receivers.
14 . The chiplet-based SiP of claim 8 , wherein:
each subset of the subsets of data receivers comprises a pair of adjacent data receivers.
15 . A method of operation in an integrated circuit (IC) chiplet, comprising:
receiving a common clock signal by a first number of multiple data receivers;
receiving data signals at substantially a same time with adjacent data receivers that form a subset of the first number of multiple data receivers, the subset of the first number of multiple data receivers comprising a second number of data receivers that is less than the first number of multiple data receivers;
coupling phase adjustment circuitry that is shared solely by the subset of the first number of multiple data receivers;
generating, with the phase adjustment circuitry, a sampling clock signal by adjusting a timing of the common clock signal to sample data signals of the adjacent data receivers.
16 . The method of claim 15 , wherein:
the adjusting of the timing of the common clock signal is based on the timing of a data signal received by at least one data receiver before being distributed to the subset of the first number of multiple data receivers.
17 . The method of claim 15 , wherein:
the receiving of the common clock signal comprises receiving a forwarded clock signal that is generated by a common clock phase adjustment circuit and forwarded from a second IC chiplet.
18 . The method of claim 17 , wherein:
the adjusting of the timing of the common clock signal comprises adjusting, with a phase interpolator of the common clock phase adjustment circuit, the timing of the common clock signal by coarse phase increments of a first phase granularity.
19 . The method of claim 18 , wherein:
the adjusting of the timing of the common clock signal further comprises adjusting, with a variable delay circuit of the phase adjustment circuitry, the timing of the common clock signal by fine phase increments of a second phase granularity that are finer than the first phase granularity.