Static random-access memory devices with angled transistors
SRAM devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to the edges of front or back faces of a support structure or a die on/in which the transistor resides, e.g., at an angle between about 10 and 80 degrees with respect to at least one of such edges. Implementing at least some of the transistors of SRAM cells as angled transistors may provide a promising way to increasing densities of SRAM cells on the limited real estate of semiconductor chips.
1 . An integrated circuit (IC) device, comprising:
a substrate having a first face and an opposing second face; and
a memory cell comprising a plurality of transistors,
wherein:
a first set of one or more transistors of the plurality of transistors is over the first face,
a second set of one or more transistors of the plurality of transistors is over the second face, coupled with one or more transistors of the first set with one or more interconnects that extend through the substrate, and
a projection of a longitudinal axis of a transistor of the first set or a transistor of the second set onto the substrate is at an angle between about 10 and 80 degrees with respect to one or more edges of the substrate.
2 . The IC device according to claim 1 , wherein the memory cell is a static random-access memory (SRAM) cell that includes storage transistors and access transistors, and wherein the storage transistors are in the first set, and the access transistors are in the second set.
3 . The IC device according to claim 1 , wherein a footprint of the second set at least partially overlaps with a footprint of the first set.
4 . The IC device according to claim 1 , wherein:
each transistor of the plurality of transistors includes a gate, a first region, and a second region,
one of the first region and the second region is a source region,
another one of the first region and the second region is a drain region,
the first set incudes transistors M 1 , M 2 , M 3 , and M 4 ,
the first region of the transistor M 1 is coupled with the first region of the transistor M 2 , and
the first region of the transistor M 3 is coupled with the first region of the transistor M 4 .
5 . The IC device according to claim 4 , wherein:
the gate of the transistor M 1 is coupled with the gate of the transistor M 2 , and
the gate of the transistor M 3 is coupled with the gate of the transistor M 4 .
6 . The IC device according to claim 5 , wherein:
each of the first region of the transistor M 1 and the first region of the transistor M 2 is coupled with a first bitline,
each of the gate of the transistor M 1 and the gate of the transistor M 2 is coupled with a second bitline,
each of the first region of the transistor M 3 and the first region of the transistor M 4 is coupled with the second bitline, and
each of the gate of the transistor M 3 and the gate of the transistor M 4 is coupled with the first bitline.
7 . The IC device according to claim 5 , wherein:
each of the first region of the transistor M 1 and the first region of the transistor M 2 is coupled with a first bitline,
each of the gate of the transistor M 1 and the gate of the transistor M 2 is coupled with a second bitline,
the first set further includes transistors M 5 and M 6 ,
each of the first region of the transistor M 1 and the first region of the transistor M 2 is coupled with the first bitline by being coupled with the first region of the transistor M 5 and the second region of the transistor M 5 being coupled with the first bitline,
each of the gate of the transistor M 1 and the gate of the transistor M 2 is coupled with the second bitline by being coupled with the first region of the transistor M 6 and the second region of the transistor M 6 being coupled with the second bitline,
each of the first region of the transistor M 3 and the first region of the transistor M 4 is coupled with the second bitline by being coupled with the first region of the transistor M 6 and the second region of the transistor M 6 being coupled with the second bitline, and
each of the gate of the transistor M 3 and the gate of the transistor M 4 is coupled with the first bitline by being coupled with the first region of the transistor M 5 and the second region of the transistor M 5 being coupled with the first bitline.
8 . The IC device according to claim 7 , wherein the gate of each of the transistor M 5 and the transistor M 6 is coupled with a wordline.
9 . The IC device according to claim 1 , wherein:
the substrate and the memory cell are part of a die, and
the IC device further includes an IC component coupled with the die.
10 . The IC device according to claim 9 , wherein the IC component includes one of a package substrate, a circuit board, an interposer, or another die.
11 . An integrated circuit (IC) device, comprising:
a die;
a first semiconductor structure over the die, the first semiconductor structure having a first portion and a second portion at an angle less than 180 degrees with respect to one another;
a second semiconductor structure over the die, the second semiconductor structure having a first portion and a second portion at an angle less than 180 degrees with respect to one another;
a plurality of transistors, each comprising a gate, a first region, and a second region, wherein one of the first region and the second region is a source region and another one of the first region and the second region is a drain region, and wherein the plurality of transistors includes transistors M 1 , M 2 , M 3 , and M 4 ;
wherein:
a channel portion of the transistor M 1 is in the first portion of the first semiconductor structure,
a channel portion of the transistor M 2 is in the first portion of the second semiconductor structure,
a channel portion of the transistor M 3 is in the second portion of the first semiconductor structure,
a channel portion of the transistor M 4 is in the second portion of the second semiconductor structure,
the first region of the transistor M 1 is coupled with the first region of the transistor M 2 ,
the gate of the transistor M 1 is coupled with the gate of the transistor M 2 ,
the first region of the transistor M 3 is coupled with the first region of the transistor M 4 , and
the gate of the transistor M 3 is coupled with the gate of the transistor M 4 .
12 . The IC device according to claim 11 , wherein each of the first portion of the first semiconductor structure, the second portion of the first semiconductor structure, the first portion of the second semiconductor structure, and the second portion of the second semiconductor structure is at an angle between 10 degrees and 80 degrees with respect to one or more edges of the die.
13 . The IC device according to claim 12 , wherein the first portion of the first semiconductor structure is substantially parallel with the first portion of the second semiconductor structure.
14 . The IC device according to claim 13 , wherein the second portion of the first semiconductor structure is substantially parallel with the second portion of the second semiconductor structure.
15 . The IC device according to claim 14 , wherein:
the first portion of the first semiconductor structure is materially continuous with the second portion of the first semiconductor structure, and
the first portion of the second semiconductor structure is materially continuous with the second portion of the second semiconductor structure.
16 . The IC device according to claim 15 , wherein:
the plurality of transistors further includes transistors M 5 and M 6 ,
a channel portion of the transistor M 5 is in the first portion of the first semiconductor structure,
a channel portion of the transistor M 6 is in the second portion of the first semiconductor structure,
the first region of the transistor M 1 is coupled with the first region of the transistor M 5 , and
the first region of the transistor M 3 is coupled with the first region of the transistor M 6 .
17 . The IC device according to claim 12 , wherein the first portion of the first semiconductor structure is substantially parallel with the second portion of the second semiconductor structure.
18 . The IC device according to claim 17 , wherein the second portion of the first semiconductor structure is substantially parallel with the first portion of the second semiconductor structure.
19 . The IC device according to claim 18 , wherein:
the first portion of the first semiconductor structure is materially continuous with the second portion of the first semiconductor structure, and
the first portion of the second semiconductor structure is materially continuous with the second portion of the second semiconductor structure.
20 . The IC device according to claim 19 , wherein:
the plurality of transistors further includes transistors M 5 and M 6 ,
a channel portion of the transistor M 5 is in the first portion of the first semiconductor structure,
a channel portion of the transistor M 6 is in the second portion of the first semiconductor structure,
the first region of the transistor M 1 is coupled with the first region of the transistor M 5 , and
the first region of the transistor M 3 is coupled with the first region of the transistor M 6 .