IP Library › Granted Patent US 12,733,217
Granted Patent B2
US 12,733,217 · App. 18/482,097 · Granted Sep 8, 2026

Gate trench power semiconductor devices having deep support shields and methods of fabricating such device

Inventors: Woongsun Kim (Cary, NC); Naeem Islam (Morrisville, NC); Madankumar Sampath (Morrisville, NC); Sei-Hyung Ryu (Cary, NC)
Assignee: Wolfspeed, Inc.
H10D62/109H10D12/031H10D30/668H10D62/393H10D62/8325H10D64/252H10P30/22
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Quick Facts
Patent No.
US 12,733,217
App. No.
18/482,097
Filed
Oct 6, 2023
Granted
Sep 8, 2026
Kind
B2
Art Unit
2893
USPC
257/77
Abstract

A semiconductor device comprises a silicon carbide based semiconductor layer structure that includes a drift layer having a first conductivity type, a gate trench that extends to a first depth into an upper surface of the semiconductor layer structure, a gate electrode in the gate trench, a support shield trench that extends to a second depth into the upper surface of the semiconductor layer structure, where the second depth is less than the first depth, and a source metallization layer on the upper surface of the semiconductor layer structure and extending into the support shield trench.

Claims (47)

1 . A semiconductor device, comprising:

a silicon carbide based semiconductor layer structure that includes a drift layer having a first conductivity type;

a gate trench that extends to a first depth into the semiconductor layer structure;

a gate electrode in the gate trench;

a support shield trench that extends to a second depth into the semiconductor layer structure, where the second depth is less than the first depth; and

a source metallization layer on the semiconductor layer structure and extending into the support shield trench,

wherein the semiconductor layer structure further comprises a source region, and the source metallization layer directly contacts both an upper surface and a side surface of the source region.

2 . The semiconductor device of claim 1 , wherein the gate electrode vertically overlaps the source region.

3 . The semiconductor device of claim 1 , wherein a maximum width of the support shield is greater than a maximum second width of the support shield trench.

4 . The semiconductor device of claim 1 , wherein the semiconductor layer structure further comprises a well contact region having a second conductivity type, and the source metallization layer directly contacts an upper surface of a portion of the well contact region that is underneath the support shield trench.

5 . The semiconductor device of claim 4 , wherein the semiconductor layer structure further comprises a support shield having the second conductivity type underneath the well contact region, where the support shield extends farther into the semiconductor layer structure than does the gate trench.

6 . The semiconductor device of claim 5 , wherein the well contact region directly contacts an upper surface of the support shield.

7 . The semiconductor device of claim 5 , wherein semiconductor layer structure further comprises:

a well region having the second conductivity type on an upper surface of the drift layer

wherein the source metallization layer directly contacts a portion of the well region that is underneath the source region.

8 . The semiconductor device of claim 5 , wherein the semiconductor layer structure further comprises a trench shielding region having the second conductivity type underneath the gate trench.

9 . The semiconductor device of claim 8 , wherein the support shield extends farther downwardly into the semiconductor layer structure than does the trench shielding region.

10 . A semiconductor device, comprising:

a silicon carbide based semiconductor layer structure;

a support shield trench in the semiconductor layer structure;

a metal layer that extends into the support shield trench;

a gate trench in the semiconductor layer structure; and

a gate electrode in the gate trench,

wherein the silicon carbide based semiconductor layer structure comprises:

a drift layer having a first conductivity type;

a well region having the second conductivity type on the drift layer;

a source region having the first conductivity type on the well region; and

a trench shielding region having the second conductivity type underneath the gate trench;

a support shield having the second conductivity type below the support shield trench and extending into the drift layer,

wherein the support shield extends deeper into the semiconductor layer structure than does the trench shielding region.

11 . The semiconductor device of claim 10 , wherein the gate trench extends farther downwardly into the semiconductor layer structure than does the support shield trench.

12 . The semiconductor device of claim 10 , wherein the metal layer directly contacts both an upper surface and a side surface of the source region.

13 . The semiconductor device of claim 10 , wherein a maximum width of the support shield is greater than a maximum second width of the support shield trench.

14 . The semiconductor device of claim 10 , wherein the semiconductor layer structure further comprises a well contact region having the second conductivity type in the well region, and wherein an upper surface of the well contact region is recessed below an upper surface of the source region.

15 . The semiconductor device of claim 14 , wherein an upper surface of the well contact region is recessed below an upper surface of the well region.

16 . A semiconductor device that includes a plurality of unit cell transistors, comprising:

a silicon carbide based semiconductor layer structure that comprises;

a drift layer having a first conductivity type;

a well region having a second conductivity type on the drift layer;

a source region having the first conductivity type on the well region; and

a well contact region having the second conductivity type in the well region, the well contact region being a portion of the well region that has a higher dopant concentration, where an upper surface of the well contact region is recessed below an upper surface of the source region;

a gate trench that extends to a first depth into an upper surface of the semiconductor layer structure;

a source metallization layer that extends in between source regions of adjacent ones of the unit cell transistors to directly contact an uppermost portion of the well contact region.

17 . The semiconductor device of claim 16 , wherein the semiconductor layer structure further comprises a support shield having the second conductivity type underneath the well contact region.

18 . The semiconductor device of claim 17 , wherein the source metallization layer directly contacts the well contact region and the well contact region directly contacts the support shield.

19 . The semiconductor device of claim 17 , wherein the source metallization layer directly contacts a side surface of the source region.

20 . The semiconductor device of claim 17 , wherein the well contact region has a first doping concentration of second conductivity type dopants that exceeds a second doping concentration of second conductivity type dopants of the well region and that also exceeds a third doping concentration of second conductivity type dopants of the support shield.

Assignments (8)
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Mar 26, 2026
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 075280/0919 →
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL AT REEL/FRAME NO. 69180/0437 Recorded Sep 30, 2025
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WOLFSPEED, INC.
Reel/Frame 072989/0088 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0113 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0381 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0467 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0588 →
SECURITY INTEREST Recorded Oct 17, 2024
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 069180/0437 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2023
From: KIM, WOONGSUN; ISLAM, NAEEM; SAMPATH, MADANKUMAR; RYU, SEI-HYUNG
To: WOLFSPEED, INC.
Reel/Frame 065316/0338 →
Continuity (1)
Related Publication 20250120133A1 · Apr 10, 2025
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