IP Library Granted Patent US 12,733,499
Granted Patent B2
US 12,733,499 · App. 17/342,307 · Granted Sep 8, 2026

Microelectronic assemblies having integrated thin film capacitors

Inventors: Kristof Kuwawi Darmawikarta (Chandler, AZ); Benjamin T. Duong (Phoenix, AZ); Srinivas V. Pietambaram (Chandler, AZ); Thomas Sounart (Chandler, AZ); Aleksandar Aleksov (Chandler, AZ); Adel A. Elsherbini (Tempe, AZ)
Assignee: Intel Corporation
H10W42/00H10D1/692H10W70/611H10W70/614H10W70/65H10W70/685H10W74/141H10W74/147H10W90/00H10W72/823H10W90/293H10W90/701H10W90/722H10W90/724
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Quick Facts
Patent No.
US 12,733,499
App. No.
17/342,307
Granted
Sep 8, 2026
Kind
B2
Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die in a first dielectric layer; and a capacitor including a first conductive pillar and a second conductive pillar in the first dielectric layer, each pillar having a first end and an opposing second end, where the first and second conductive pillars form a first plate of the capacitor; a second dielectric layer on the die and on the second end of the first and second conductive pillars extending at least partially along a first thickness of the first and second conductive pillars and tapering from the second end towards the first end; and a metal layer on the second dielectric layer, wherein the metal layer extends at least partially along a second thickness of the first and second conductive pillars, where the metal layer forms a second plate of the capacitor.

Claims (34)

1 . A microelectronic assembly, comprising:

a die, having a first surface and an opposing second surface, in a first dielectric layer; and

an embedded metal-insulator-metal (MIM) capacitor, the MIM capacitor including:

a first conductive pillar, having a first end and an opposing second end, in the first dielectric layer;

a second conductive pillar, having a first end and an opposing second end, in the first dielectric layer, wherein the first and second conductive pillars form a first plate of the capacitor;

a second dielectric layer on the second surface of the die and on the second end of the first and second conductive pillars, wherein the second dielectric layer extends at least partially along a first thickness of the first and second conductive pillars and tapers from the second end towards the first end; and

a metal layer on the second dielectric layer, wherein the metal layer extends at least partially along a second thickness of the first and second conductive pillars, wherein the second thickness is less than the first thickness, and wherein the metal layer forms a second plate of the capacitor.

2 . The microelectronic assembly of claim 1 , wherein the die is a first die, and further comprising:

a redistribution layer (RDL) on the metal layer; and

a second die in a third dielectric layer on the RDL, wherein the metal layer is electrically coupled to the second die via conductive pathways in the RDL.

3 . The microelectronic assembly of claim 1 , wherein the die is a first die, and further comprising:

a redistribution layer (RDL) on the metal layer; and

a second die in a third dielectric layer on the RDL, wherein the second ends of the first and second pillars are electrically coupled to the second die via conductive pathways in the RDL.

4 . The microelectronic assembly of claim 1 , further comprising:

a third conductive pillar in the first dielectric layer electrically coupled to the metal layer.

5 . The microelectronic assembly of claim 1 , wherein the second dielectric layer has a taper between 80 degrees and 90 degrees.

6 . The microelectronic assembly of claim 1 , further comprising:

a package substrate, wherein the first ends of the first and second conductive pillars are electrically coupled to the package substrate.

7 . The microelectronic assembly of claim 1 , wherein a material of the second dielectric layer includes a high-k dielectric material.

8 . The microelectronic assembly of claim 1 , wherein a thickness of the second dielectric layer is between 5 nanometers and 1 micron.

9 . The microelectronic assembly of claim 1 , wherein a material of the metal layer includes one or more of a metal, a metal oxide, or a metal alloy.

10 . The microelectronic assembly of claim 1 , wherein a thickness of the metal layer is between 10 nanometers and 15 microns.

11 . An embedded metal-insulator-metal (MIM) capacitor for an integrated circuit (IC) device, comprising:

a first MIM capacitor plate, including:

a first conductive pillar, having a first end and an opposing second end, in a first dielectric layer; and

a second conductive pillar, having a first end and an opposing second end, in the first dielectric layer;

a second dielectric layer on the second end of the first and second conductive pillars, wherein the second dielectric layer extends at least partially along a first thickness of the first and second conductive pillars and tapers from the second end towards the first end; and

a second MIM capacitor plate, including a metal layer on the second dielectric layer, wherein the metal layer extends at least partially along a second thickness of the first and second conductive pillars, and wherein the second thickness is less than the first thickness.

12 . The embedded MIM capacitor of claim 11 , further comprising:

a third conductive pillar in the first dielectric layer electrically coupled to the metal layer.

13 . The embedded MIM capacitor of claim 11 , wherein the second dielectric layer has a taper between 80 degrees and 90 degrees.

14 . The embedded MIM capacitor of claim 11 , wherein a pitch of the first and second conductive pillars is between 100 microns and 500 microns.

15 . The embedded MIM capacitor of claim 11 , further comprising:

a package substrate, wherein the first ends of the first and second conductive pillars are electrically coupled to the package substrate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076007/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2021
From: DARMAWIKARTA, KRISTOF KUWAWI; DUONG, BENJAMIN T.; PIETAMBARAM, SRINIVAS V.; SOUNART, THOMAS; ALEKSOV, ALEKSANDAR; ELSHERBINI, ADEL A.
To: INTEL CORPORATION
Reel/Frame 056473/0801 →
Continuity (1)
Related Publication 20220392855A1 · Dec 8, 2022
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