Systems and methods for performing independent plane concurrent memory operations in non-volatile memory structures
Method for performing a memory operation with respect to a memory structure having “N”-number of planes, each plane comprising “M”-number of blocks and “X”-number of word lines arranged in a serial order, and electrically connected with each plane are: a voltage bias source, an electronic switching component, and row decoder, the method comprising: with respect to each plane, selecting a block and a word line for application of the operation, wherein the operation has not been applied to the selected block and word line, the selected block of one plane is located in a different block group from the selected block of another plane, and the selected word line of one plane is in a different position within the serial order from a position of the selected word line of another plane; and using the voltage bias source, concurrently applying the operation to the selected blocks and selected word lines.
1 . A method for performing a multi-plane memory operation with respect to a multi-plane memory structure, wherein the multi-plane memory operation includes programming multiple memory planes in a same programming operation, the method comprising:
initiating a memory operation with respect to a memory system, wherein:
the memory system comprises a non-volatile memory structure having a plurality of memory planes, with each memory plane comprising: (1) a plurality of memory blocks, and (2) a plurality of word lines arranged in a serial order; and
electrically connected with each memory plane are: (1) a respective voltage bias source from among a plurality of plane-independent voltage bias sources, (2) at least one electronic switching component, and (3) at least one row decoder;
with respect to each memory plane, selecting a respective memory block and a respective word line for application of the memory operation, wherein:
the memory operation has not yet been applied to the selected memory block and the selected word line;
the selected memory block of one memory plane is located in a different memory block group from the selected memory block of another memory plane; and
the selected word line of one memory plane can be in a different position within the serial order from a position of the selected word line of another memory plane;
in a first mode, using the respective voltage bias sources, concurrently applying the memory operation to the respective selected memory blocks and to the respective selected word lines,
wherein the respective voltage bias sources comprise multiple voltage bias sources, wherein each of the respective voltage bias sources is associated with a specific one of the memory planes, and
in a second mode, performing an asynchronous memory operation in which a starting time of the application of the memory operation with respect to one memory plane differs from a starting time of the application of the memory operation to another memory plane by applying respective voltage biases to the memory planes from the plurality of plane-independent voltage bias sources.
2 . The method according to claim 1 , wherein the memory structure comprises a plurality of NAND-type memory cells, and:
at least one of the memory blocks comprises a population of SLC-type memory cells; and
at least one of the other memory blocks comprises a population of memory cells having a higher storage density than an SLC-type memory cell.
3 . The method according to claim 1 , wherein a memory block group comprises all memory blocks located within a same memory array row.
4 . A memory controller configured to perform a multi-plane memory operation in which multiple memory planes are programmed in a same programming operation, the memory controller comprising:
a communication pathway configured to couple to a memory system, wherein:
the memory system comprises a non-volatile memory structure having a plurality of memory planes, with each memory plane comprising: (1) a plurality of memory blocks, and (2) a plurality of word lines arranged in a serial order, and
electrically connected with each memory plane are: (1) a respective voltage bias source from among a plurality of plane-independent voltage bias sources; (2) at least one electronic switching component, and (3) at least one row decoder;
the memory controller is configured to:
initiate a memory operation with respect to the memory system;
with respect to each memory plane, select a respective memory block and a respective word line for application of the memory operation, wherein:
the memory operation has not yet been applied to the selected memory block and the selected word line;
the selected memory block of one memory plane can be located in a different memory block group from the selected memory block of another memory plane; and
the selected word line of one memory plane can be in a different position within the serial order from a position of the selected word line of another memory plane;
in a first mode, using the respective voltage bias sources, concurrently apply the memory operation to the respective selected memory blocks and to the respective selected word lines,
wherein the voltage bias source comprises multiple voltage bias sources, wherein each voltage bias source is associated with a specific one of the memory planes; and
in a second mode, performing an asynchronous memory operation in which a starting time of the application of the memory operation with respect to one memory plane differs from a starting time of the application of the memory operation to another memory plane by applying respective voltage biases to the memory planes from the plurality of plane-independent voltage bias sources.
5 . The memory controller according to claim 4 , wherein the memory structure comprises a plurality of NAND-type memory cells, and:
at least one of the memory blocks comprises a population of SLC-type memory cells; and
at least one of the other memory blocks comprises a population of memory cells having a higher storage density than an SLC-type memory cell.
6 . The memory controller according to claim 4 , wherein a memory block group comprises all memory blocks located within a same memory array row.
7 . A non-volatile memory system configured to perform a multi-plane memory operation in which multiple memory planes are programmed in a same programming operation, comprising:
a memory structure having an a plurality of memory planes, with each memory plane comprising: (1) a plurality of memory blocks, and (2) a plurality of word lines arranged in a serial order;
electrically connected with each memory plane: (1) a respective voltage bias source from among a plurality of plane-independent voltage bias sources; (2) at least one electronic switching component, and (3) at least one row decoder;
a memory controller coupled to the memory structure and configured to:
initiate a memory operation with respect to the memory system;
with respect to each memory plane, select a respective memory block and a respective word line for application of the memory operation, wherein:
the memory operation has not yet been applied to the selected memory block and the selected word line;
the selected memory block of one memory plane can be located in a different memory block group from the selected memory block of another memory plane; and
the selected word line of one memory plane can be in a different position within the serial order from a position of the selected word line of another memory plane;
in a first mode, using the respective voltage bias sources, concurrently apply the memory operation to the respective selected memory blocks and to the respective selected word lines,
wherein the voltage bias source comprises multiple voltage bias sources, wherein each voltage bias source is associated with a specific one of the memory planes; and
in a second mode, performing an asynchronous memory operation in which a starting time of the application of the memory operation with respect to one memory plane differs from a starting time of the application of the memory operation to another memory plane by applying respective voltage biases to the memory planes from the plurality of plane-independent voltage bias sources.
8 . The non-volatile memory system according to claim 7 , wherein the memory structure comprises a plurality of NAND-type memory cells, and:
at least one of the memory blocks comprises a population of SLC-type memory cells; and
at least one of the other memory blocks comprises a population of memory cells having a higher storage density than an SLC-type memory cell.
9 . The non-volatile memory system according to claim 7 , wherein a memory block group comprises all memory blocks located within a same memory array row.