IP Library › Granted Patent US 6,885,436
Granted Patent B1
US 6,885,436 · App. 10/243,562 · Granted Apr 26, 2005

Optical error minimization in a semiconductor manufacturing apparatus

Assignee: LSI Logic Corporation
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Quick Facts
Patent No.
US 6,885,436
App. No.
10/243,562
Granted
Apr 26, 2005
Kind
B1
Abstract

Provided are systems and methods for overcoming optical errors occurring from reticle and other hardware usage in a semiconductor fabrication apparatus. The systems and methods minimize optical errors, such as those resulting from gravitational sag on a reticle or mask, for a pattern being projected onto a wafer. The reduced errors allow larger reticles and masks to be used—while maintaining optical accuracy; and also improve optical budget management.

Claims (32)

1. A semiconductor fabrication apparatus for producing a photolithographic image on a wafer, the apparatus comprising:

a light source that emits light for transmission onto the wafer;

a reticle that transmits a portion of the light emitted by the light source and produces the photolithographic image; and

means for minimizing optical errors arising from hardware usage in the semiconductor fabrication apparatus wherein the means for minimizing optical errors comprises a reticle construction that includes a non-planar surface configured to compensate for gravitational sag in the reticle while the reticle rests on a reticle stage.

2. The reticle of claim 1 wherein the reticle is constructed with a substantially non-planar surface and wherein said substantially non-planar reticle surface comprises the means for minimizing optical errors by compensating for deformation resulting from gravitational sag.

3. The reticle of claim 2 wherein the reticle is constructed with an upward arc that compensates for deformation resulting from gravitational sag.

4. The reticle of claim 2 wherein the substantially non-planar reticle surface is achieved by polishing the surface to obtain the substantially non-planar reticle surface.

5. The reticle of claim 4 wherein the substantially non-planar reticle surface is achieved by molding the reticle surface to obtain the substantially non-planar reticle surface.

6. The reticle of claim 2 wherein the substantially non-planar reticle surface includes a curved top surface of the reticle.

7. The reticle of claim 2 wherein the substantially non-planar reticle surface includes a curved bottom surface of the reticle.

8. The reticle of claim 2 wherein both a top surface and a bottom surface of the reticle comprise substantially non-planar reticle surfaces.

9. The reticle of claim 2 wherein the semiconductor fabrication apparatus includes an upper chamber and a lower chamber which are separated by the reticle and a seal and wherein a differential pressure is generated across the reticle achieved by one of raising and lowering a pressure in one of the lower chamber and the upper chamber thereby inducing a deformation in the reticle to compensate for the effects of gravitational sag in the reticle thereby reducing optical errors in an image projected on the wafer by the reticle.

10. The reticle of claim 1 wherein the retical construction includes a reticle having a substantially non-planar reticle top surface and a substantially planar reticle bottom surface, the surfaces being configured to compensate for gravitational sag in the reticle while the reticle rests on the reticle stage.

11. The reticle of claim 1 wherein the retical construction includes a reticle having a substantially non-planar reticle bottom surface and a substantially planar reticle top surface, the surfaces being configured to compensate for gravitational sag in the reticle while the reticle rests on the reticle stage.

12. A semiconductor fabrication apparatus for producing a photolithographic image on a wafer, the apparatus comprising:

a light source that emits light for transmission onto the wafer;

a reticle that transmits a portion of the light emitted by the light source and produces the photolithographic image; and

means for minimizing optical errors arising from hardware usage in the semiconductor fabrication apparatus wherein the means for minimizing optical errors comprises a pellicle bonded to the reticle such that the combined reticle and pellicle structure minimizes any optical errors for the image projected on the wafer by the reticle.

13. The semiconductor fabrication apparatus of claim 12 wherein the pellicle increases the aggregate stiffness of the combined reticle and pellicle structure.

14. The semiconductor fabrication apparatus of claim 12 wherein the pellicle includes a transparent membrane and an outer frame along an outer portion of the reticle wherein the outer frame of the pellicle increases the aggregate stiffness of the combined reticle and pellicle structure.

15. The semiconductor fabrication apparatus of claim 14 wherein the pellicle frame is configured to apply a torque to the reticle to offset the effects of gravitational sag in the reticle.

16. A semiconductor fabrication apparatus for producing a photolithographic image on a wafer, the apparatus comprising:

a light source that emits light for transmission onto the wafer;

a reticle that transmits a portion of the light emitted by the light source and produces the photolithographic image;

means for minimizing optical errors arising from hardware usage in the semiconductor fabrication apparatus wherein the means for minimizing optical errors comprises a pressure regulation system within the semiconductor fabrication apparatus that provides a differential pressure across the reticle, wherein the differential pressure minimizes any optical errors for the image projected on the wafer by the reticle; and

wherein the operation of the pressure regulation system is monitored and controlled using feedback from an interferometric monitoring system.

17. A semiconductor fabrication apparatus for producing a photolithographic image on a wafer, the apparatus comprising:

a light source that emits light for transmission onto the wafer;

a reticle that transmits a portion of the light emitted by the light source and produces the photolithographic image;

means for minimizing optical errors arising from hardware usage in the semiconductor fabrication apparatus wherein the means for minimizing optical errors comprises a pressure regulation system within the semiconductor fabrication apparatus that provides a differential pressure across the reticle, wherein the differential pressure minimizes any optical errors for the image projected on the wafer by the reticle; and

wherein the pressure regulation system includes an upper sealed chamber and a lower sealed chamber separated by the reticle and by a seal configured to enable pressure regulation system to provide a differential pressure across the reticle, wherein the differential pressure enables the correction of gravitational sag in the reticle.

18. The semiconductor fabrication apparatus of claim 17 wherein the operation of the pressure regulation system is monitored and controlled using feedback from an interferometric monitoring system.

Assignments (12)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 060885/0001 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2002
From: BERMAN, MICHAEL J.; BAILEY, GEORGE E.
To: LSI LOGIC CORPORATION
Reel/Frame 013310/0948 →