IP Library Granted Patent US 9,691,739
Granted Patent B2
US 9,691,739 · App. 15/061,444 · Granted Jun 27, 2017

Semiconductor device and method of manufacturing same

Inventors: Michihiro Kawashita (Hitachinaka, JP); Yasuhiro Yoshimura (Kasumigaura, JP); Naotaka Tanaka (Kasumigaura, JP); Takahiro Naito (Duesseldorf, DE); Takashi Akazawa (Musashimurayama, JP)
Assignee: Tessera Advanced Technologies, Inc.
H01L25/0657H01L21/6835H01L21/76898H01L23/481H01L23/528H01L23/5226H01L23/5386H01L24/11H01L24/12H01L24/13H01L24/16H01L24/27H01L24/81H01L24/94H01L25/074H01L25/50H01L2221/68372H01L2224/0401H01L2224/0557H01L2224/05557H01L2224/05572H01L2224/06181H01L2224/1147H01L2224/11472H01L2224/13009H01L2224/13012H01L2224/13013H01L2224/13014H01L2224/13021H01L2224/13022H01L2224/13025H01L2224/13099H01L2224/16058H01L2224/16112H01L2224/16146H01L2224/274H01L2224/81136H01L2224/81345H01L2224/81365H01L2224/81801H01L2224/81898H01L2225/06513H01L2225/06517H01L2225/06541H01L2924/0002H01L2924/00014H01L2924/01002H01L2924/014H01L2924/01005H01L2924/01006H01L2924/01013H01L2924/01018H01L2924/01022H01L2924/01024H01L2924/01028H01L2924/01029H01L2924/01033H01L2924/01074H01L2924/01078H01L2924/01079H01L2924/10253H01L2924/1205H01L2924/1306H01L2924/14H01L2924/1451H01L2924/19041H01L2924/30107
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,691,739
App. No.
15/061,444
Filed
Mar 4, 2016
Granted
Jun 27, 2017
Kind
B2
Examiner
ROMAN, ANGEL
Art Unit
2817
USPC
257/774
Abstract

In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a first semiconductor substrate having a first surface and a second surface opposite the first surface, a first insulating film formed on the first surface, a first hole formed in the first insulating film and partially extending into the first semiconductor substrate, a second hole formed in the second surface, a first electrode entirely filling the first hole, and a conductive film conformally formed in the second hole. The conductive film is electrically connected to a bottom surface of the first electrode and leaves a third hole in the first semiconductor substrate open. The third hole is configured to receive a second electrode of a second semiconductor substrate.

Claims (57)

1. A semiconductor device comprising:

a first chip comprising:

a first semiconductor substrate having a first surface and a second surface opposite the first surface;

a first insulating film formed on the first surface;

a first hole formed in the first insulating film and partially extending into the first semiconductor substrate;

a second hole formed in the second surface;

a single-piece first electrode entirely filling the first hole and comprising a portion that extends above the first insulating film, wherein at least some of the portion of the first electrode that extends above the first insulating film is disposed over at least a portion of the first insulating film; and

a first conductive film conformally formed in the second hole, the first conductive film being electrically connected to a bottom surface of the first electrode and leaving a third hole in the first semiconductor substrate open; and

a second chip comprising a third electrode;

wherein the third electrode is inserted into the third hole and makes electrical contact with the first conductive film.

2. The semiconductor device of claim 1 , wherein the first chip further comprises a protective insulating film formed at a boundary portion between the first electrode and the first semiconductor substrate, the protective insulating film insulating the first electrode and the first semiconductor substrate from each other.

3. The semiconductor device of claim 1 , wherein the first chip further comprises a second insulating film formed at a boundary portion between the first conductive film and the first semiconductor substrate, the second insulating film electrically insulating the first conductive film and the first semiconductor substrate from each other.

4. The semiconductor device of claim 1 , wherein the portion of the first electrode that extends above the first insulating film has a tapered shape.

5. The semiconductor device of claim 1 , wherein the portion of the first electrode that extends above the first insulating film is configured to be shaped by plastic deformation.

6. The semiconductor device of claim 1 , wherein the first conductive film is further connected to a side surface of the first electrode.

7. The semiconductor device of claim 1 , wherein, in a planar view, a diameter of the first electrode extending into the first semiconductor substrate is smaller than a diameter of the second hole.

8. The semiconductor device of claim 1 , further comprising a pad formed between the first insulating film and the first electrode.

9. The semiconductor device of claim 1 , wherein the third electrode is configured to be shaped by plastic deformation upon insertion into the third hole.

10. The semiconductor device of claim 1 , further comprising:

a third chip comprising:

a third semiconductor substrate having a third surface;

a second insulating film formed on the third surface;

a fourth hole formed in the second insulating film and extending into the third semiconductor substrate; and

a second conductive film conformally formed in the fourth hole and leaving a fifth hole in the third semiconductor substrate open;

wherein the first electrode is inserted into the fourth hole and makes electrical contact with the second conductive film.

11. A semiconductor device comprising:

a first chip comprising:

a first semiconductor substrate having a first surface and a second surface opposite the first surface;

a first insulating film formed on the first surface;

a first hole formed in the first insulating film and partially extending into the first semiconductor substrate;

a second hole formed in the second surface;

a single-piece first electrode entirely filling the first hole and comprising a portion that extends above the first insulating film, wherein at least some of the portion of the first electrode that extends above the first insulating film is disposed over at least a portion of the first insulating film; and

a first conductive film conformally formed in the second hole, the first conductive film being electrically connected to a bottom surface of the first electrode and leaving a third hole in the first semiconductor substrate open; and

a second chip comprising:

a second semiconductor substrate having a third surface;

a second insulating film formed on the third surface;

a fourth hole formed in the second insulating film and extending into the second semiconductor substrate; and

a second conductive film conformally formed in the fourth hole and leaving a fifth hole in the second semiconductor substrate open;

wherein the portion of the first electrode that extends above the first insulating film is inserted into the fifth hole and makes electrical contact with the second conductive film.

12. The semiconductor device of claim 11 , wherein the first chip further comprises a third insulating film formed at a boundary portion between the first electrode and the first semiconductor substrate, the third insulating film insulating the first electrode and the first semiconductor substrate from each other.

13. The semiconductor device of claim 11 , wherein the first chip further comprises a third insulating film formed at a boundary portion between the first conductive film and the first semiconductor substrate, the third insulating film electrically insulating the first conductive film and the first semiconductor substrate from each other.

14. The semiconductor device of claim 11 , wherein the portion of the first electrode that extends above the first insulating film has a tapered shape.

15. The semiconductor device of claim 11 , wherein the portion of the first electrode that extends above the first insulating film is configured to be shaped by plastic deformation upon insertion into the fifth hole.

16. The semiconductor device of claim 11 , wherein the first conductive film is further connected to a side surface of the first electrode.

17. A semiconductor device comprising:

a first chip comprising:

a first semiconductor substrate having a first surface and a second surface opposite the first surface;

an insulating film formed on the second surface;

a first hole extending through the first semiconductor substrate from the first surface to the second surface; and

a single-piece first electrode formed to partially fill the first hole so that a first portion of the first hole is left open to the first surface, the first electrode comprising a second portion that extends above the second surface and the insulating film, wherein at least some of the second portion of the first electrode that extends above the insulating film is disposed over at least a portion of the insulating film; and

a second chip comprising:

a second semiconductor substrate having a third surface; and

a second hole open to the third surface;

wherein the first chip and the second chip are connected by deforming the second portion of the first electrode that extends above the second surface into the second hole.

18. The semiconductor device of claim 17 , wherein:

the second chip further comprises a second electrode at least partially filling the second hole; and

the second portion of the first electrode makes electrical contact with the second electrode.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
MERGER Recorded Apr 4, 2017
From: RENESAS TECHNOLOGY CORP.
To: NEC ELECTRONICS CORPORATION
Reel/Frame 042157/0071 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2017
From: KAWASHITA, MICHIHIRO; YOSHIMURA, YASUHIRO; TANAKA, NAOTAKA; NAITO, TAKAHIRO; AKAZAWA, TAKASHI
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 041846/0283 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2017
From: RENESAS TECHNOLOGY CORP.
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 042157/0183 →
CHANGE OF NAME Recorded Apr 4, 2017
From: NEC ELECTRONICS CORPORATION
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 042154/0964 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Priority Claims (1)
JP 2008-323581 · Dec 19, 2008 · national
Continuity (5)
Continuation 14716791 · May 19, 2015
Continuation 14464026 · Aug 20, 2014
Continuation 13340165 · Dec 29, 2011
Continuation 12640766 · Dec 17, 2009
Related Publication 20160190102A1 · Jun 30, 2016