Semiconductor system, device and structure
An Integrated Circuit device, including: first transistors and second transistors, where the first transistors and the second transistors each include a single crystal channel, where at least one of the second transistors overlays at least one of the first transistors with less than 1 micron distance apart, and where at least one of the second transistors is a dopant segregated schottky barrier transistor.
1. A 3D semiconductor device, the device comprising:
a first single crystal layer comprising a plurality of first transistors;
at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates;
a plurality of through silicon vias (TSVs);
at least one connection from said plurality of first transistors to a plurality of through silicon vias (TSVs);
a plurality of second transistors overlaying said at least one metal layer;
a plurality of third transistors overlaying said plurality of second transistors,
wherein said plurality of second transistors are self-aligned to said plurality of third transistors having been processed following the same lithography step; and
a first memory array and a second memory array,
wherein said first memory array comprises said plurality of second transistors and said second memory array comprises said plurality of third transistors,
wherein at least one of said plurality of second transistors comprises a polysilicon channel,
wherein at least one of said plurality of second transistors is junction-less transistor,
wherein each of said plurality of second transistors comprises a gate, and
wherein formation of said gate comprises Atomic Layer Deposition (ALD).
2. The 3D semiconductor device according to claim 1 , further comprising:
wherein at least one of said third transistors is a double gate transistor, and
wherein each gate of said double gate transistor is independently controlled.
3. The 3D semiconductor device according to claim 1 , further comprising:
a NAND type flash memory comprising said first memory array.
4. The 3D semiconductor device according to claim 1 , further comprising:
a top metal layer overlaying said plurality of third transistors; and
a plurality of fourth transistors overlaying said top metal,
wherein a subset of said plurality of first transistors are part of peripheral circuit controlling said first memory array.
5. The 3D semiconductor device according to claim 1 ,
wherein each of said plurality of second transistors comprises a gate dielectric, and
wherein said gate dielectric comprises a low temperature microwave plasma oxide.
6. The 3D semiconductor device according to claim 1 ,
wherein at least one of said first transistors is of the dopant segregated schottky barrier type.
7. The 3D semiconductor device according to claim 1 ,
wherein at least one of said plurality of second transistors directly overlays at least one of said TSVs.
8. A 3D semiconductor device, the device comprising:
a first single crystal layer comprising a plurality of first transistors;
at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates;
a plurality of through silicon vias (TSVs);
at least one connection from said plurality of first transistors to a plurality of through silicon vias (TSVs);
a plurality of second transistors overlaying said at least one metal layer;
a plurality of third transistors overlaying said plurality of second transistors,
wherein said plurality of second transistors are self-aligned to said plurality of third transistors having been processed following the same lithography step; and
a first memory array and a second memory array,
wherein said first memory array comprises said plurality of second transistors and said second memory array comprises said plurality of third transistors,
wherein at least one of said plurality of second transistors comprises a polysilicon channel, and
wherein at least one of said plurality of second transistors is junction-less transistor.
9. The 3D semiconductor device according to claim 8 ,
wherein at least one of said second transistors is a double gate transistor, and
wherein each gate of said double gate transistor is independently controlled.
10. The 3D semiconductor device according to claim 8 ,
wherein at least one of said first transistors is of the dopant segregated schottky barrier type.
11. The 3D semiconductor device according to claim 8 , further comprising:
a NAND type flash memory comprising said first memory array.
12. The 3D semiconductor device according to claim 8 , further comprising:
a top metal layer overlaying said plurality of third transistors; and
a plurality of fourth transistors overlaying said top metal,
wherein a subset of said plurality of first transistors are part of peripheral circuit controlling said first memory array.
13. The 3D semiconductor device according to claim 8 ,
wherein said plurality of fourth transistors are part of a memory periphery circuit.
14. A 3D semiconductor device, the device comprising:
a first single crystal layer comprising a plurality of first transistors;
at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates;
a plurality of through silicon vias (TSVs);
at least one connection from said plurality of first transistors to a plurality of through silicon vias (TSVs);
a plurality of second transistors overlaying said at least one metal layer;
a plurality of third transistors overlaying said plurality of second transistors,
wherein said plurality of second transistors are self-aligned to said plurality of third transistors having been processed following the same lithography step; and
a first memory array and a second memory array,
wherein said first memory array comprises said plurality of second transistors and said second memory array comprises said plurality of third transistors.
15. The 3D semiconductor device according to claim 14 ,
wherein at least one of said plurality of second transistors comprises a polysilicon channel.
16. The 3D semiconductor device according to claim 14 ,
wherein at least one of said second transistors is a double gate transistor, and
wherein each gate of said double gate transistor is independently controlled.
17. The 3D semiconductor device according to claim 14 ,
wherein at least one of said first transistors is of the dopant segregated schottky barrier type.
18. The 3D semiconductor device according to claim 14 ,
wherein at least one of said plurality of second transistors is a junction-less transistor.
19. The 3D semiconductor device according to claim 14 , further comprising:
a NAND type flash memory comprising said plurality of second transistors.
20. The 3D semiconductor device according to claim 14 , further comprising:
a top metal layer overlaying said plurality of third transistors; and
a plurality of fourth transistors overlaying said top metal,
wherein a subset of said plurality of first transistors are part of peripheral circuit controlling said first memory array.