Semiconductor packages with an intermetallic layer
A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.
1. A semiconductor package, comprising:
a plurality of exposed pads on a top side of a die;
a passivation layer on the top side of the die surrounding each exposed pad; and
a bump coupled to each of the plurality of exposed pads;
wherein each bump comprises a titanium sublayer, a nickel sublayer, and one of a silver and tin intermetallic layer or a copper and tin intermetallic layer, the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer having a melting temperature greater than 260 degrees Celsius;
wherein the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer is formed by reflowing a tin layer and one of a silver layer or copper layer with a silver layer of a substrate;
wherein the substrate is directly coupled onto the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer, the substrate comprising a copper layer that was directly coupled onto the silver layer before the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer was reflowed.
2. The package of claim 1 , wherein an intervening layer was coupled between the nickel sublayer and a copper layer in the copper and tin intermetallic layer before the copper and tin intermetallic layer was reflowed.
3. The package of claim 1 , wherein the nickel sublayer is between the titanium sublayer and one of the silver and tin intermetallic layer or the copper and tin intermetallic layer.
4. The package of claim 1 , wherein the passivation layer comprises one of an oxide, nitride, or polyimide.
5. The package of claim 1 , wherein the semiconductor package comprises a flip chip.
6. A semiconductor package, comprising:
a plurality of bumps on a top side of a die;
wherein each bump comprises a titanium sublayer, a nickel sublayer, and one of a silver and tin intermetallic layer or a copper and tin intermetallic layer, the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer having a melting temperature greater than 260 degrees Celsius;
wherein the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer is formed by reflowing a tin layer and one of a silver layer or copper layer with a silver layer of a substrate;
wherein the substrate is directly coupled onto the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer, the substrate comprising a copper layer that was directly coupled onto the silver layer before the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer was reflowed.
7. The package of claim 6 , wherein an intervening layer was coupled between the nickel sublayer and a copper layer in the copper and tin intermetallic layer before the copper and tin intermetallic layer was reflowed.
8. The package of claim 6 , wherein the nickel sublayer is between the titanium sublayer and one of the silver and tin intermetallic layer or the copper and tin intermetallic layer.
9. The package of claim 6 , further comprising a plurality of pads coupled between the plurality of bumps and the die.
10. The package of claim 9 , further comprising a passivation layer comprising one of an oxide, nitride, or polyimide coupled around each pad of the plurality of pads.
11. The package of claim 6 , wherein the semiconductor package comprises a flip chip.
12. A semiconductor package, comprising:
a plurality of bumps on a top side of a die;
wherein each bump comprises a titanium sublayer, a nickel sublayer, and one of a silver and tin reflowed intermetallic layer or a copper and tin reflowed intermetallic layer, the one of the silver and tin reflowed intermetallic layer or the copper and tin reflowed intermetallic layer having a melting temperature greater than 260 degrees Celsius;
wherein a substrate is directly coupled onto the one of the silver and tin reflowed intermetallic layer or the copper and tin reflowed intermetallic layer, the substrate comprising a copper layer that was directly coupled onto a silver layer before the one of the silver and tin reflowed intermetallic layer or copper and tin reflowed intermetallic layer was reflowed.
13. The package of claim 12 , wherein an intervening layer was coupled between the nickel sublayer and a copper layer in the copper and tin intermetallic layer before the copper and tin intermetallic layer was reflowed.
14. The package of claim 12 , wherein the nickel sublayer is between the titanium sublayer and one of the silver and tin intermetallic layer or the copper and tin intermetallic layer.
15. The package of claim 12 , further comprising a plurality of pads coupled between the plurality of bumps and the die.
16. The package of claim 15 , further comprising a passivation layer coupled over the die and surrounding each pad of the plurality of pads.
17. The package of claim 16 , wherein the passivation layer comprises one of an oxide, nitride, or polyimide.
18. The package of claim 12 , wherein the semiconductor package comprises a flip chip.