IP Library › Assignment 012653/0747
Patent Assignment
Reel/Frame 012653/0747

Security Interest

Recorded: 2002-04-12 Pages: 17
Assignor
RAMTRON INTERNATIONAL CORPORATION
Executed: 2002-03-28
Assignee
INFINEON TECHNOLOGIES AG
ST. MARTIN STRASSE 53, D-81541 MUNICH, GERMANY
Covered Properties (139)
Monolithic Semiconductor Integrated Circuit Ferroelectric Memory Device, and Methods of Fabricating and Utilizing Same
Patent: 4,707,897 →
Application: 06/133,338 →
Combined Integrated Circuit/Ferroelectric Memory Device, and Ion Beam Methods of Constructing Same
Patent: 4,713,157 →
Application: 06/733,939 →
Method of Making Ferroelectric Memory Devices
Patent: 5,024,964 →
Application: 06/793,186 →
Self Restoring Ferroelectric Memory
Patent: 4,873,664 →
Application: 07/013,746 →
Data Storage Device and Method of Using a Ferroeloctric Capacitance Divider
Patent: 4,853,893 →
Application: 07/069,389 →
Method of Operating a Memory Cell with Volatile and Non-Volatile Portions Having Ferroelectric Capacitors
Patent: 4,809,225 →
Application: 07/069,390 →
Timepiece Communication System
Patent: 4,800,543 →
Application: 07/128,550 →
Ferroelectric Retention Method
Patent: 4,893,272 →
Application: 07/184,996 →
Non-Volatile Memory Cell and Sensing Method
Patent: 4,888,733 →
Application: 07/243,414 →
One Transistor Memory Cell with Programmable Capacitance Divider
Patent: 4,914,627 →
Application: 07/292,776 →
Sram with Programmable Capacitance Divider
Patent: 4,918,654 →
Application: 07/292,818 →
Dram with Programmable Capacitance Divider
Patent: 4,910,708 →
Application: 07/292,891 →
Multilayer Electrodes for Integrated Circuit Capacitors
Patent: 5,005,102 →
Application: 07/368,668 →
Dram Memory Cell and Method of Operation Thereof for Transferring Increased Amount of Charge to a Bit Line
Patent: 5,109,357 →
Application: 07/491,180 →
Sealed Self Aligned Contacts Using Two Nitrides Process
Patent: 5,043,790 →
Application: 07/505,242 →
Trench Capacitor for Large Scale Integrated Memory
Patent: 5,075,817 →
Application: 07/542,573 →
Method for Creating Self-Aligned, Non-Patterned Contact Areas & Stacked Capacitors Using the Method
Patent: 5,104,822 →
Application: 07/559,466 →
Output Control Circuit Having Continuously Variable Drive Current
Patent: 5,255,222 →
Application: 07/644,902 →
Current Supply Circuit for Driving High Capacitance Load in an Integrated Circuit
Patent: 5,134,310 →
Application: 07/644,903 →
Reference Generator for an Integrated Circuit
Patent: 5,117,177 →
Application: 07/644,904 →
Stacked Capacitor with Sidewall Insulation
Patent: 5,162,890 →
Application: 07/681,159 →
Reaction Barrier for a Multilayer Structure in an Integrated Circuit
Patent: 5,170,242 →
Application: 07/698,841 →
Conducting Electrode Layers for Ferroelectric Capacitors in Integrated Circuits and Method
Patent: 5,142,437 →
Application: 07/714,682 →
Self Sealed Aligned Contact Incorporating a Dopant Source
Patent: 5,216,281 →
Application: 07/750,098 →
Monolithic Semiconductor Integrated Circuit Ferroelectric Memory Device
Patent: 5,214,300 →
Application: 07/763,371 →
Semiconductor Device with Ferroelectric and Method of Manufacturing the Same
Patent: 5,293,510 →
Application: 07/778,895 →
Structure of High Dielectric Constant Metal/ Dielectric/Semiconductor Capacitor for Use as the Storage Capacitor in Memory Devices
Patent: 5,338,951 →
Application: 07/788,547 →
Series Ferroelectric Capacitor Structure for Monolithic Integrated Circuits and Method
Patent: 5,206,788 →
Application: 07/806,726 →
Method of Manufacturing Semiconductor Device Using a Ferroelectric Film Over a Source Region
Patent: 5,229,309 →
Application: 07/828,886 →
Structure and Method for Increasing the Dielectric Constant of Integrated Ferroelectric Capacitors
Patent: 5,216,572 →
Application: 07/853,901 →
Use of Palladium as an Adhesion Layer and as an Electrode in Ferroelectric Memory Devices
Patent: 5,191,510 →
Application: 07/875,749 →
Non-Volatile Ferroelectric Memory with Folded Bit Lines and Method of Making the Same
Patent: 5,371,699 →
Application: 07/977,825 →
Sealed Self Aligned Contact Process
Patent: 5,385,634 →
Application: 08/043,569 →
Ozone Gas Processing for Ferroelectric Memory Circuits
Patent: 5,374,578 →
Application: 08/064,746 →
Ferroelectric-Based Ram Sensing Scheme Including Bit-Line Capacitance Isolation
Patent: 5,381,364 →
Application: 08/083,883 →
Ferroelectrid Memory Device with Capacitor Electrode in Direct Contact with Source Region
Patent: 5,866,926 →
Application: 08/093,790 →
Semiconductor Device Having a Ferroelectric Film in a Through-Hole
Patent: 5,369,296 →
Application: 08/139,340 →
Ferroelectric Capacitor Renewal Method
Patent: 5,525,528 →
Application: 08/200,216 →
System and Method for Write-Protecting Predetermined Portions of a Memory Array
Patent: 5,394,367 →
Application: 08/210,699 →
Passivation Method and Structure for a Ferroelectric Integrated Circuit Using Hard Ceramic Materials or the Like
Patent: 5,438,023 →
Application: 08/212,495 →
Semiconductor Device Having a Transistor, a Ferroelectric Capacitor and a Hydrogen Barrier Film
Patent: 5,523,595 →
Application: 08/238,802 →
Noise and Glitch Suppressing Filter with Feedback
Patent: 5,479,132 →
Application: 08/254,281 →
System and Method for Initiating Communications Between a Controller and a Selected Subset of Multiple Transponders in a Common Rf Field
Patent: 5,434,572 →
Application: 08/255,088 →
Stacked Ferroelectric Memory Cell and Method
Patent: 5,495,117 →
Application: 08/257,954 →
Method of Manufacturing Ferroelectric Bismuth Layered Oxides
Patent: 5,426,075 →
Application: 08/259,870 →
Process for Fabricating Transistors Using Composite Nitride Structure
Patent: 5,610,099 →
Application: 08/267,278 →
Circuit with a Single Address Register That Augments a Memory Controller by Enabling Cache Reads and Page-Mode Writes
Patent: 5,566,318 →
Application: 08/284,384 →
Layered Local Interconnect Compatible with Integrated Circuit Ferroelectric Capacitors
Patent: 5,498,569 →
Application: 08/294,077 →
Semiconductor Device with a Conductive Reaction-Preventing Film
Patent: 5,475,248 →
Application: 08/303,134 →
Voltage Reference for a Ferroelectric 1T/1C Based Memory
Patent: 5,572,459 →
Application: 08/306,686 →
Enhanced Dram with All Reads from on-Chip Cache and All Writers to Memory Array
Patent: 5,699,317 →
Application: 08/319,289 →
Passivation Method and Structure Using Hard Ceramic Materials or the Like
Patent: 5,578,867 →
Application: 08/394,467 →
Film Having Ferroelectric Bismuth Layered Oxides
Patent: 5,519,566 →
Application: 08/403,489 →
Ferroelectric Memory Sensing Method Using Distinct Read and Write Voltages
Patent: 5,532,953 →
Application: 08/413,083 →
Circuit and Method for Reducing a Compensation of a Ferroelectric Capacitor by Multiple Pulsing of the Plate Line Following a Write Operation
Patent: 5,592,410 →
Application: 08/420,293 →
Ferroelectric Memory Sensing Scheme Using Bit Lines Precharged to a Logic One Voltage
Patent: 5,530,668 →
Application: 08/420,752 →
Enhanced Dram with Single Row Sram Cache for All Device Read Operations
Patent: 5,721,862 →
Application: 08/460,665 →
Low Loss, Regulated Charge Pump with Integrated Ferroelectric Capacitors
Patent: 5,889,428 →
Application: 08/468,861 →
Ferroelectric Nonvolatile Random Access Memory Utilizing Self-Bootstrapping Plate Line Segment Drivers
Patent: 5,598,366 →
Application: 08/515,558 →
Programmable Output Devices for Controlling Signal Levels in an Rf/Id Transponder
Patent: 5,926,110 →
Application: 08/521,251 →
Multibus Cached Memory System
Patent: 5,802,560 →
Application: 08/521,597 →
Integration of High Value Capacitor with Ferroelectric Memory
Patent: 5,608,246 →
Application: 08/525,497 →
Method for Making a Ferroelectrric Memory Cell with a Ferroelectric Capacitor Overlying a Memory Transistor
Patent: 5,580,814 →
Application: 08/527,175 →
Method of Making Integration of High Value Capacitor with Ferro- Electric Memory
Patent: 5,909,624 →
Application: 08/544,470 →
Computer Hybrid Memory Including Dram and Edram Memory Components, with Secondary Cache in Edram for Dram
Patent: 5,875,451 →
Application: 08/615,392 →
Use of Calcium and Strontium Dopants to Improve Retention Performance in a Pzt Ferroelectric Film
Patent: 5,969,935 →
Application: 08/616,856 →
Method of Measuring Retention Performance and Imprint Degradation of Ferroelectric Films
Patent: 6,008,659 →
Application: 08/616,913 →
Iridium Oxide Local Interconnect
Patent: 5,838,605 →
Application: 08/618,884 →
Edram with Integrated Generation and Control of Write Enable and Column Latch Signals and Method for Making Same
Patent: 5,835,442 →
Application: 08/620,450 →
Bootstrapping Circuit Utilizing a Ferroelectric Capacitor
Patent: 5,774,392 →
Application: 08/620,799 →
Ed Ram Having a Dynamically-Sized Cache Memory and Associated Method Thereof
Patent: 5,983,313 →
Application: 08/630,489 →
Voltage Reference for a Ferroelectric 1T/Ic Based Memory
Patent: 5,822,237 →
Application: 08/634,445 →
Low Voltage Bootstrapping Circuit
Patent: 5,999,461 →
Application: 08/663,032 →
Circuit and Method for Reducing Compensation of a Ferroelectric Capacitor by Multiple Pulsing of the Plate Line Following a Write Operation
Patent: 5,815,430 →
Application: 08/691,132 →
Completely Encapsulated Top Electrode of a Ferroelectric Capacitor
Patent: 5,920,453 →
Application: 08/700,076 →
Bandgap Reference Based Power-on Detect Circuit Including a Supression Circuit
Patent: 5,852,376 →
Application: 08/702,363 →
Semiconductor Memory Device
Patent: 5,818,771 →
Application: 08/723,367 →
Same State and Opposite State Diagnostic Test for Ferroelectric Memories
Patent: 5,661,730 →
Application: 08/723,935 →
Yield Enhancement Technique for Integrated Circuit Processing to Reduce Effects of Undesired Dielectric Moisture Retention and Subsequent Hydrogen Out-Diffusion
Patent: 5,990,513 →
Application: 08/728,256 →
Partially or Completely Encapsulated Top Electrode of a Ferroelectric Capacitor
Patent: 5,864,932 →
Application: 08/728,740 →
Data Processor Incorporating a Ferroelectric Memory Array Selectably Configurable as Read/Write and Read Only Memory
Patent: 5,890,199 →
Application: 08/734,802 →
System and Method Providing Selective Write Protection for Individual Blocks of Memory in a Non-Volatile Memory Device
Patent: 5,802,583 →
Application: 08/745,581 →
Low-Power Non-Resetable Test Mode Circuit
Patent: 5,804,996 →
Application: 08/799,999 →
Serial Ferroelectric Random Access Memory Architecture to Equalize Column Accesses and Improve Data Retention Reliability by Mitigating Imprint Effects
Patent: 5,912,846 →
Application: 08/810,607 →
System and Method for Mitigating Imprint Effect in Ferroelectric Random Access Memories Utilizing a Complementary Data Path
Patent: 5,745,403 →
Application: 08/810,608 →
Partially or Completely Encapsulated Top Electrode of a Ferroelectric Capacitor
Patent: 6,027,947 →
Application: 08/828,157 →
First-In, First-Out Integrated Circuit Memory Device Utilizing a Dynamic Random Access Memory Array for Data Storage Implemented in Conjuction with an Associated Static Random Access Memory Cache
Patent: 5,901,100 →
Application: 08/840,118 →
Enhanced Signal Processing Random Access Memory Device Utilizing a Dram Memory Array Integrated with an Associated Sram Cache and Internal Refresh Control
Patent: 5,991,851 →
Application: 08/850,802 →
Dual-Level Metalization Method for Integrated Circuit Ferroelectric Devices
Patent: 5,902,131 →
Application: 08/853,527 →
Use of Calcium and Strontium Dopants to Improve Retention Performance in a Pzt Ferroelectric Film
Patent: 5,800,683 →
Application: 08/861,674 →
Enhanced Dram with Embedded Registers
Patent: 5,887,272 →
Application: 08/888,371 →
Multi-Layer Approach for Optimizing Ferroelectric Film Performance
Patent: 6,080,499 →
Application: 08/896,684 →
Voltage Boost Circuit and Operation Thereof at Low Power Supply Voltages
Patent: 5,854,568 →
Application: 08/915,054 →
Plate Line Segmentation in a 1T/1C Ferroelectric Memory
Patent: 5,995,406 →
Application: 08/970,448 →
Reference Cell for a 1T/1C Ferroelectric Memory
Patent: 5,956,266 →
Application: 08/970,452 →
Sensing Methodology for a 1T/1C Ferroelectric Memory
Patent: 5,880,989 →
Application: 08/970,453 →
Column Decoder Configuration for a 1T/1C Ferroelectric Memory
Patent: 5,892,728 →
Application: 08/970,454 →
Reference Cell Configuration for a 1T/1C Ferroelectric Memory
Patent: 5,986,919 →
Application: 08/970,518 →
Sense Amplifier Configuration for a 1T/1C Ferroelectric Memory
Patent: 5,969,980 →
Application: 08/970,519 →
Memory Cell Configuration for a 1T/1C Ferroelectric Memory
Patent: 6,028,783 →
Application: 08/970,520 →
Sense Amplifier Latch Driver Circuit for a 1T/1C Erroelectric Memory
Patent: 6,002,634 →
Application: 08/970,521 →
Plate Line Driver Circuit for a 1T/1C Ferroelectric Memory
Patent: 5,978,251 →
Application: 08/970,522 →
Bandgap Reference Based Power-on Detect Circuit Including a Suppression Circuit
Patent: 5,867,047 →
Application: 09/017,577 →
Integrated Circuit Memory Device Incorporating a Non-Volatile Memory Array and a Relatively Faster Access Time Memory Cache
Patent: 6,263,398 →
Application: 09/021,132 →
Sense Amplifier Utilizing a Balancing Resistor
Patent: 5,901,088 →
Application: 09/022,106 →
Ferroelectric Thin Films and Solutions: Compositions
Patent: 6,203,608 →
Application: 09/061,362 →
Multi-Layer Approach for Optimizing Ferroelectric Film Performance
Patent: 6,090,443 →
Application: 09/064,465 →
Technique for Reducing Element Disable Fuse Pitch Requirements in an Integrated Circuit Device Incorporating Replaceable Circuit Elements
Patent: 6,141,281 →
Application: 09/069,468 →
Completely Encapsulated Top Electrode of a Ferroelectric Capacitor Using a Lead-Enhanced Escapsulation Layer
Patent: 6,211,542 →
Application: 09/085,280 →
Cmos Rc Equivalent Delay Circuit
Patent: 6,097,231 →
Application: 09/087,726 →
Plastic Package Assembly Method for a Ferroelectric-Based Integrated Circuit
Patent: 6,232,153 →
Application: 09/090,575 →
Embedded Enhanced Dram, and Associated Method
Patent: 5,963,481 →
Application: 09/108,089 →
Multi-Array Memory Device, and Associated Method, Having Shared Decoder Circuitry
Patent: 6,064,620 →
Application: 09/111,822 →
Dynamic Random Access Memory Word Line Boost Technique Employing a Boost-on-Writes Policy
Patent: 6,055,192 →
Application: 09/146,726 →
Hydrogen Barrier Encapsulation Techniques for the Control of Hydrogen Induced Degradation of Ferroelectric Capacitors in Conjunction with Multilevel Metal Processing for Non-Volatile Integrated Circuit Memory Devices
Patent: 6,249,014 →
Application: 09/164,952 →
Method of Manufacturing Ferroelectric Memory Device Useful for Preventing Hydrogen Line Degradation
Patent: 6,174,735 →
Application: 09/177,392 →
Multi-Bank Esdram with Cross -Coupled Sram Cache Registers
Patent: 6,249,840 →
Application: 09/178,298 →
Enhanced Dram with Embedded Registers
Patent: 6,347,357 →
Application: 09/182,994 →
Method of Forming Oxide Local Interconnect
Patent: 5,985,713 →
Application: 09/183,545 →
Cmos Preferred State Power-Up Latch
Patent: 6,060,919 →
Application: 09/205,033 →
Integrated Circuit Memory Device and Method Incorporating Flash and Ferroelectric Random Access Memory Arrays
Patent: 6,249,841 →
Application: 09/205,538 →
Double Data Rate Synchronous Dynamic Random Access Memory Device Incorporating a Static Ram Cache Per Memory Bank
Patent: 6,330,636 →
Application: 09/236,804 →
First-In, First-Out Integrated Circuit Memory Device Incorporating a Retransmit Function
Patent: 6,072,741 →
Application: 09/266,472 →
Barrier Layer to Protect a Ferroelectric Capacitor After Contact Has Been Made to the Capacitor Electrode
Patent: 6,242,299 →
Application: 09/283,166 →
Polarization Method for Minimizing the Effects of Hydrogen Damage on Ferroelectric Thin Film Capacitors
Patent: 6,238,933 →
Application: 09/305,949 →
Ferroelectric Non-Volatile Latch Circuits
Patent: 6,141,237 →
Application: 09/351,563 →
Yield Enhancement Technique for Integrated Circuit Processing to Reduce Effects of Undesired Dielectric Moisture Retention and Subsequent Hydrogen Out-Diffusion
Patent: 6,190,926 →
Application: 09/356,534 →
Multi-Layer Approach for Optimizing Ferroelectric Film Performance
Patent: 6,287,637 →
Application: 09/427,644 →
Plate Line Driver Circuit for a 1T/1C Ferroelectric Memory
Patent: 6,185,123 →
Application: 09/465,724 →
Method of Fabricating Partially or Completely Encapsulated Top Electrode of a Ferroelectric Capacitor
Patent: 6,150,184 →
Application: 09/505,106 →
Enhanced bus turnaround integrated circuit dynamic random access memory device
Patent: 6,151,236 →
Application: 09/515,007 →
Multi-array memory device, and associated method, having shared decoder circuitry
Patent: 6,278,646 →
Application: 09/533,923 →
First-In, first-out integrated circuit memory device incorporating a retransmit function
Patent: 6,172,927 →
Application: 09/536,072 →
Ferroelectric memory device structure useful for preventing hydrogen line degradation
Patent: 6,201,726 →
Application: 09/588,153 →
Enhanced bus turnaround integrated circuit dynamic random access memory device
Patent: 6,301,183 →
Application: 09/626,623 →
Method of Manufacturing Ferroelectric Memory Device Structure Useful for Preventing Hydrogen Line Degradation
Patent: 6,358,755 →
Application: 09/641,091 →
Reference cell configuration for a 1T/1C ferroelectric memory
Patent: 6,252,793 →
Application: 09/663,121 →
Ferroelectric voltage boost circuits
Patent: 6,275,425 →
Application: 09/714,879 →
Completely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced encapsulation layer
Patent: 6,281,023 →
Application: 09/759,128 →
Publication: US 2001/0001488
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. May 14, 1985
From: MC MILLAN, LARRY; PAZ DE ARAUJO, CARLOS
To: RAMTRON CORPORATION A CORP OF DE
Reel/Frame 004421/0626 →
Assignment of Assignors Interest. Oct 31, 1985
From: ROHRER, GEORGE A.; MC MILLAN, LARRY D.
To: RAMTRON CORPORATION, A CORP OF DE
Reel/Frame 004481/0611 →
Assignment of Assignors Interest. Aug 22, 1988
From: EATON, S. SHEFFIELD JR.; BUTLER, DOUGLAS; PARRIS, MICHAEL C.
To: RAMTRON CORPORATION, A CORP. OF DE
Reel/Frame 004931/0860 →
Assignment of Assignors Interest. Sep 12, 1988
From: MOBLEY, KENNETH J.
To: RAMTRON CORPORATION, A CORP. OF DE.
Reel/Frame 004935/0075 →
Assignment of Assignors Interest. Sep 19, 1988
From: PAZ DE ARAUJO, CARLOS
To: RAMTRON CORPORATION, A CORP. OF DE
Reel/Frame 004993/0760 →
Assignment of Assignors Interest. Sep 19, 1988
From: LYNDON-JAMES, ROSS
To: RAMTRON CORPORATION, A CORP. OF DE
Reel/Frame 004993/0762 →
Assignment of Assignors Interest. Sep 19, 1988
From: GNADINGER, ALFRED P.
To: RAMTRON CORPORATION, A CORP. OF DE
Reel/Frame 004993/0766 →
Assignment of Assignors Interest. Sep 19, 1988
From: BLACK, DONALD L.
To: RAMTRON CORPORATION, A CORP. OF DE
Reel/Frame 004993/0764 →
Assignment of Assignors Interest. Jun 20, 1989
From: LARSON, WILLIAM L.
To: RAMTRON CORPORATION
Reel/Frame 005095/0171 →
Assignment of Assignors Interest. Apr 5, 1990
From: BUTLER, DOUGLAS
To: RAMTRON CORPORATION, A CORP. OF DE; NMB SEMICONDUCTOR COMPANY, LTD., A CORP. OF JAPAN
Reel/Frame 005282/0415 →
Assignment of 1/2 of Assignors Interest Jun 22, 1990
From: BUTLER, DOUGLAS B.
To: RAMTRO CORPORATION, A CORP. OF DE; NMB SEMICONDUCTOR COMPANY, LTD., A CORP. OF JAPAN
Reel/Frame 005345/0818 →
Assignment of Assignors Interest. Each Assignee to Own an Undivided One-Half Interest Jul 30, 1990
From: BUTLER, DOUGLAS B.
To: RAMTRON CORPORATION, A CORP. OF DE; NMB SEMICONDUCTOR COMPANY, LTD., A CORP. OF JAPAN
Reel/Frame 005398/0413 →
Assignment of Assignors Interest. Jan 23, 1991
From: EATON, S. S. JR.
To: RAMTRON CORPORATION, A CORP. OF DELAWARE; NMB SEMICONDUCTOR CO., LTD.
Reel/Frame 005588/0771 →
Assignment of Assignors Interest. Jan 23, 1991
From: MOBLEY, KENNETH J.
To: RAMTRON CORPORATION, A CORP. OF DE; NMB SEMICONDUCTOR CO., LTD.
Reel/Frame 005599/0578 →
Assignment of Assignors Interest. Jan 23, 1991
From: EATON, S. S. JR.
To: RAMTRON CORPORATION, A CORP. OF DE; NMB SEMICONDUCTOR CO., LTD., JAPAN
Reel/Frame 005590/0958 →
Assignment of Assignors Interest. Jun 13, 1991
From: KAMMERDINER, LEE; HUFFMAN, MARIA; GOLABI-KHOOZANI, MANOOCHEHR
To: RAMTRON CORPORATION, A DE CORPORATION
Reel/Frame 005738/0501 →
Assignment of Assignors Interest. Oct 28, 1991
From: BUTLER, DOUGLAS
To: RAMTRON CORPORATION A CORP. OF DELAWARE; NMB SEMICONDUCTOR COMPANY, LTD. A CORP. OF JAPAN
Reel/Frame 005898/0548 →
Merger May 10, 1993
From: RAMTRON CORPORATION
To: RAMTRON INTERNATIONAL CORPORATION
Reel/Frame 006581/0001 →
Change of Name May 28, 1993
From: NMB SEMICONDUCTOR COMPANY, LTD.
To: NIPPON STEEL SEMICONDUCTOR CORPORATION
Reel/Frame 006554/0575 →
Security Interest Oct 12, 1993
From: RAMTRON INTERNATIONAL CORPORATION
To: NATIONAL ELECTRICAL BENEFIT FUND; BENTON, OREN L.
Reel/Frame 006721/0286 →
Security Interest Mar 3, 1995
From: RAMTRON INTERNATIONAL CORPORATION
To: NATIONAL ELECTRICAL BENEFIT FUND
Reel/Frame 007374/0032 →
Security Agreement Sep 29, 1995
From: RAMTRON INTERNATIONAL CORPORATION
To: NATIONAL ELECTRICAL BENEFIT FUND
Reel/Frame 007662/0353 →
Release/Termination of Security Interest Sep 29, 1995
From: NATIONAL ELECTRICAL BENEFIT FUND; BENTON, OREN L.
To: RAMTRON INTERNATIONAL CORPORATION
Reel/Frame 007648/0966 →
Release of Security Interest Mar 29, 2004
From: NATIONAL ELECTRICAL BENEFIT FUND
To: RAMTRON INTERNATIONAL CORPORATION
Reel/Frame 014468/0248 →
Amendment to Security Agreement and Amendment to Certain Ip Apr 5, 2004
From: INFINEON TECHNOLOGIES AG
To: RAMTRON INTERNATIONAL CORPORATION
Reel/Frame 014491/0364 →