IP Library Assignment 049629/0170
Patent Assignment
Reel/Frame 049629/0170

Change of Name

Recorded: 2019-06-28 Pages: 3
Assignor
POWERCHIP SEMICONDUCTOR CORP.
Executed: 2010-08-09
Assignee
POWERCHIP TECHNOLOGY CORPORATION
NO.12, LI-HSIN ROAD 1, HSINCHU SCIENCE PARK,, HSINCHU, TAIWAN
Covered Properties (20)
Wafer Prober for in-Line Cleaning Probe Card
Patent: 6,420,891 →
Application: 09/640,184 →
Semiconductor Device Having Reduced Interconnect-Line Parasitic Capacitance
Patent: 6,531,776 →
Application: 09/940,852 →
Publication: US 2002/0132466
Method for Forming Stepped Contact Hole for Semiconductor Devices
Patent: 6,444,574 →
Application: 09/948,485 →
Method of Forming Stepped Contact Trench for Semiconductor Devices
Patent: 6,583,055 →
Application: 10/057,142 →
Method of Fabricating Memory Device
Patent: 6,696,350 →
Application: 10/064,140 →
Publication: US 2003/0232484
Structure, Fabrication and Operation Method of Flash Memory Device
Patent: 6,628,550 →
Application: 10/064,143 →
Split-Gate Flash Memory Structure and Method of Manufacture
Patent: 6,794,710 →
Application: 10/064,883 →
Publication: US 2003/0230775
Method of Manufacturing Semiconductor Device
Patent: 6,670,254 →
Application: 10/065,298 →
Trench Flash Memory Device and Method of Fabricating Thereof
Patent: 6,870,212 →
Application: 10/065,345 →
Publication: US 2004/0067618
Structure, Fabrication Method and Operation Method of Flash Memory
Patent: 6,770,925 →
Application: 10/065,553 →
Publication: US 2004/0084718
Structure of Flash Memory Device and Fabrication Method Thereof
Patent: 6,730,959 →
Application: 10/065,554 →
Publication: US 2004/0084716
Method for Reading Flash Memory with Silicon-Oxide/Nitride/Oxide-Silicon (Sonos) Structure
Patent: 6,639,836 →
Application: 10/065,565 →
Automatic Production Quality Control Method and System
Patent: 6,766,208 →
Application: 10/211,452 →
Publication: US 2003/0060916
Method of Cleaning a Probe Card
Patent: 6,659,847 →
Application: 10/231,774 →
Publication: US 2003/0060131
Method of Manufacturing High Coupling Ratio Flash Memory Having Sidewall Spacer Floating Gate Electrode
Patent: 6,875,660 →
Application: 10/248,867 →
Publication: US 2004/0166641
Silicon-On-Insulator Device with Control Transistor
Patent: 6,828,633 →
Application: 10/248,868 →
Publication: US 2004/0089899
Flash Memory with Self-Aligned Split Gate and Methods for Fabricating and for Operating the Same
Patent: 6,765,260 →
Application: 10/249,024 →
Flash memory cell including two floating gates and an erasing gate
Patent: 6,855,598 →
Application: 10/249,059 →
Publication: US 2004/0180495
Method for Automatically Controlling Defect -Specification in a Semiconductor Manufacturing Process
Patent: 6,807,454 →
Application: 10/249,103 →
Publication: US 2003/0212469
Single-Poly Eprom and Method for Forming the Same
Patent: 6,653,183 →
Application: 10/269,602 →
Publication: US 2003/0203575
Related Assignments (4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jul 12, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049732/0110 →
Assignment of Assignor's Interest Jul 12, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049732/0121 →
Assignment of Assignor's Interest Apr 8, 2020
From: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 052337/0735 →
Assignment of Assignor's Interest Sep 7, 2020
From: POWERCHIP TECHNOLOGY CORPORATION
To: NEXCHIP SEMICONDUCTOR CORPORATION
Reel/Frame 053704/0522 →