Parallel CRC computation with data enables

1. A communication system, comprising:

a server coupled to a communication medium by way of a media access controller (MAC) and a physical layer device (PHY), the MAC including a transmit path for formatting information for transmission over the communication medium by the physical layer device and a receive path for formatting data sequences, provided by the PHY, for use by the server, the MAC additionally including a cyclic redundancy check (CRC) block for generating a cyclic redundancy check (CRC) on parallel input data having data enables, the parallel input data having N bits, the cyclic redundancy check using a CRC polynomial having p bits, the CRC block comprising:

a plurality of preconditioning blocks coupled to at least a portion of an input word and at least a portion of an intermediate CRC value, each preconditioning block configured to generate bitwise exclusive OR values of values from the input word and values from the intermediate CRC value, and to append n-p zeros to the most-significant bit position of the bitwise exclusive OR values, n being the number of bits of the input word coupled to the preconditioning block, and wherein the preconditioning blocks coupled to only a portion of the input word are further configured to append N-n zeros to the least-significant bit position of the bitwise exclusive OR values;

a first selector coupled to the preconditioning blocks and configured to select the bitwise exclusive OR values from one of the preconditioning blocks;

a CRC modulo block coupled to the first selector and configured to generate a CRC value for the selected bitwise exclusive OR values;

a second selector coupled to a portion of the intermediate CRC value and selecting zero values and values from the portion of the intermediate CRC value;

an exclusive OR block coupled to the CRC modulo block and the second selector and configured to generate bitwise exclusive OR values of the CRC value from the CRC modulo block and the selected values from the second selector;

a register coupled to the exclusive OR block and configured to save the generated generate bitwise exclusive OR values; and

a third selector coupled to the registered value and an initial value, the second selector configured to supply the registered value or the initial value as the intermediate CRC value.