Differential amplifier and low drop-out regulator with thereof
View Patent ↗A differential amplifier having a positive input terminal, a negative input terminal, an output terminal, a bias terminal and a ground terminal is provided. The differential amplifier comprises a differential pair circuit and a current mirror circuit. Wherein, the differential pair circuit is coupled to the positive input terminal, the negative input terminal, the output terminal, and the bias terminal of the differential amplifier. The current mirror circuit receives a constant current from a current source, and mirrors the constant current to the differential pair circuit. The current mirror circuit further connects to the ground terminal of the differential amplifier, and the terminal of the current mirror circuit receiving the constant current is coupled to a first source/drain terminal of a first PMOS transistor. A second source/drain and a gate of the first PMOS transistor are connected to the bias terminal and the output terminal of the differential amplifier, respectively.
1. A low drop-out (LDO) regulator, comprising:
a differential amplifier circuit having a positive input terminal, a negative input terminal, an output terminal, a bias terminal and a ground terminal, comprising:
a differential pair circuit electrically coupled to the negative input terminal and the output terminal, receiving an input voltage from the positive input terminal, and electrically coupled to a positive bias through the bias terminal;
a current source for providing a constant current;
a current mirror circuit for receiving the constant current and mirroring the constant current to the differential pair circuit, and the current mirror circuit being grounded through the ground terminal; and
a first PMOS transistor having a first source/drain terminal electrically coupled to the current mirror circuit for receiving the constant current, a second source/drain terminal electrically coupled to the positive bias through the bias terminal, and a gate electrically coupled to the output terminal;
a first passive element having a first terminal being grounded, and a second terminal electrically coupled to the negative input terminal; and
a second PMOS transistor having a first source/drain terminal electrically coupled to the negative input terminal and the second terminal of the first passive element, a gate electrically coupled to the output terminal, and a second source/drain terminal electrically coupled to the positive bias.
2. The low drop-out regulator of claim 1 , wherein the differential pair circuit comprises:
a first NMOS transistor having a first source/drain terminal electrically coupled to the current mirror circuit for receiving the constant current mirrored by the current mirror circuit, a gate electrically coupled to the positive input terminal, and a second source/drain terminal electrically coupled to the output terminal;
a second NMOS transistor having a gate electrically coupled to the negative input terminal, and a first source/drain terminal electrically coupled to the first source/drain terminal of the first NMOS transistor;
a third PMOS transistor having a first source/drain terminal electrically coupled to the second source/drain terminal of the first NMOS transistor, and a second source/drain terminal electrically coupled to the positive bias through the bias terminal; and
a fourth PMOS transistor having a first source/drain terminal electrically coupled to a gate thereof, a second source/drain terminal of the second NMOS transistor, and a gate of the third PMOS transistor respectively, and a second source/drain terminal electrically coupled to the positive bias through the bias terminal.
3. The low drop-out regulator of claim 1 , wherein the current mirror circuit comprises:
a third NMOS transistor having a first source/drain terminal being grounded through the ground terminal, and a second source/drain terminal electrically coupled to the differential pair circuit; and
a fourth NMOS transistor having a first source/drain terminal being grounded, a second source/drain terminal receiving the constant current, and a gate electrically coupled to the gate of the third NMOS transistor.
4. The low drop-out regulator of claim 1 , wherein a parasitic capacitor is connected between the output terminal of the differential amplifier circuit and the second PMOS transistor.
5. The low drop-out regulator of claim 1 , wherein the first passive element is a resistor.
6. The low drop-out regulator of claim 1 , further comprising a second passive element having a first terminal electrically coupled to the negative input terminal and the second terminal of the first passive element, and a second terminal electrically coupled to the first source/drain terminal of the second PMOS transistor.
7. The low drop-out regulator of claim 6 , wherein the second passive element is a resistor.