Differential voltage mode driver and digital impedance caliberation of same

1. A differential driver circuit having at least one driver stage comprising:

an input coupled by a pre-driver to:

a gate of a first PMOS transistor in parallel with a first NMOS transistor, where a source of the first PMOS transistor is coupled to a drain of the first NMOS transistor, and a drain of the first PMOS transistor is coupled to a source of the first NMOS transistor;

a gate of a second NMOS transistor having a drain coupled to the drain of the first PMOS transistor and a source coupled to a ground; and

a gate of a third NMOS transistor;

a first differential output coupled to the drain of the second NMOS transistor;

the input coupled by an inverting pre-driver to:

a gate of a second PMOS transistor in parallel with the third NMOS transistor, where a source of the second PMOS transistor is coupled to a drain of the third NMOS transistor, and a drain of the second PMOS transistor is coupled to a source of the third NMOS transistor;

a gate of the first NMOS transistor; and

a gate of a fourth NMOS transistor having a drain coupled to the drain of the second PMOS transistor and a source coupled to the ground; and

a second differential output coupled to the drain of the fourth NMOS transistor;

wherein the source of the first PMOS transistor is coupled to a voltage source;

wherein the source of the second PMOS transistor is coupled to the voltage source; and

wherein the voltage source is configured to provide a voltage signal indicative of a predetermined peak to peak output voltage.

2. The differential driver circuit of claim 1 , further comprising a plurality of the at least one driver stages coupled in parallel.

3. The differential driver circuit of claim 2 , further comprising a calibration circuit configured to activate a number of the plurality of parallel driver stages such that an impedance of the plurality of parallel driver stages approximately matches an impedance of a transmission line coupled to the differential driver.

4. The differential driver circuit of claim 1 , wherein the voltage source is an external power supply.

5. The differential driver circuit of claim 1 , wherein the voltage source comprises an internal voltage regulator.

6. A method of calibrating a differential driver circuit having a plurality of parallel n-type driver stages and a plurality of parallel p-type driver stages, the differential driver circuit for driving a differential signal over a transmission line having an impedance, the method comprising:

determining an indication of an impedance of a plurality of parallel n-type replica stages, wherein the plurality of parallel n-type replica stages are replicas of the plurality of parallel n-type driver stages;

determining a number of the plurality of parallel n-type replica stages to approximately match the determined indication of impedance of a plurality of parallel n-type replica stages with the transmission line impedance;

activating a number of the plurality of parallel n-type driver stages equal to the number of the plurality of parallel n-type replica stages;

determining an indication of an impedance of a plurality of parallel p-type replica stages, wherein the plurality of parallel p-type replica stages are replicas of the plurality of parallel p-type driver stages;

determining a number of the plurality of parallel p-type replica stages to approximately match the determined indication of impedance of a plurality of parallel p-type replica stages with the transmission line impedance; and

activating a number of the plurality of parallel p-type driver stages equal to the number of the plurality of parallel p-type replica stages; and

wherein the determining the indication of the impedance of the plurality of parallel n-type replica stages comprises:

measuring a voltage at a node of a first voltage divider comprising the plurality of parallel n-type replica stages in series with a first resistor having a predetermined resistance;

comparing the voltage at the node of the first voltage divider to a first reference voltage having a first predetermined voltage;

wherein the determining the number of the plurality of parallel n-type replica stages to approximately match the measured impedance of a plurality of parallel n-type replica stages with the transmission line impedance comprises:

increasing, decreasing or maintaining the number of the plurality of parallel n-type replica stages based on the comparing the voltage at the node of the first voltage divider to the first reference voltage;

wherein the determining the indication of the impedance of the plurality of parallel p-type replica stages comprises:

measuring a voltage at a node of a second voltage divider comprising the plurality of parallel p-type replica stages in series with a second resistor having the predetermined resistance;

comparing the voltage at the node of the second voltage divider to a second reference voltage having a predetermined voltage; and

wherein the determining the number of the plurality of parallel p-type replica stages to approximately match the measured impedance of a plurality of parallel p-type replica stages with the transmission line impedance comprises:

increasing, decreasing or maintaining the number of the plurality of parallel p-type replica stages based on the comparing the voltage at the node of the second voltage divider to the second reference voltage.

7. The method of claim 6 : wherein the first and second voltage is dividers are coupled to a voltage source and to a ground;

wherein the first reference voltage is a first percentage of the voltage source;

wherein the second reference voltage is a second percentage of the voltage source;

wherein the first percentage of the voltage source and the predetermined resistance are predetermined such that the comparing the voltage at the node of the first voltage divider to the first reference voltage having a first predetermined voltage reflects a comparison of the impedance of the plurality of the parallel n-type replica stages and the transmission line impedance; and

wherein the second percentage of the voltage source and the predetermined resistance are predetermined such that the comparing the voltage at the node of the second voltage divider to the second reference voltage having a second predetermined voltage reflects a comparison of the impedance of the plurality of the parallel p-type replica stages and the transmission line impedance.

8. The method of claim 7 , wherein the first reference voltage is about twenty-five percent of the voltage source and the second reference voltage is about seventy-five percent of the voltage source.

9. The method of claim 6 , wherein the increasing, decreasing or maintaining, the number of the plurality of parallel n-type replica stages based on the comparing the voltage at the node of the first voltage divider to the first reference voltage is performed by a first finite state machine configured to count up, to count down, or to maintain the number of the plurality of parallel n-type replica stages; and

wherein the increasing, decreasing or maintaining the number of the plurality of parallel p-type replica stages based on the comparing the voltage at the node of the second voltage divider and the second reference voltage is performed by a second finite state machine configured to count up, to count down, or to maintain, the number of the plurality of parallel p-type replica stages.

10. The method of claim 6 ,

wherein each p-type driver stage comprises a PMOS transistor in parallel with an NMOS transistor; and

wherein each n-type driver stage comprises an NMOS transistor.

11. A circuit for calibrating a differential driver circuit configured to drive a differential signal over a transmission line having an impedance, the circuit comprising:

the differential driver circuit comprising an H-bridge circuit comprising:

a plurality of parallel n-type driver stages coupled to a driver logic circuitry; and

a plurality of parallel p-type driver stages coupled to the driver logic circuitry;

an n-type calibration circuit comprising:

a plurality of parallel n-type replica stages having an impedance, wherein the plurality of parallel n-type replica stages are replicas of the plurality of parallel n-type driver stages;

a first resistor coupled with the plurality of parallel n-type replica stages at a first node;

a first comparator configured to generate a first signal indicative of a comparison of a voltage at the first node with a first reference voltage; and

first logic circuitry coupled to the first comparator and to the plurality of parallel n-type replica stages, the first logic circuitry configured to determine, based on the first comparison signal, a first number (N) of the plurality of parallel n-type replica stages to approximately match the impedance of the plurality of the parallel n-type replica stages and the transmission line impedance; and

wherein the driver logic circuitry is configured to activate N of the plurality of parallel n-type driver stages;

a p-type calibration circuit comprising:

a plurality of parallel p-type replica stages having an impedance, wherein the plurality of parallel p-type replica stages are replicas of the plurality of parallel p-type driver stages;

a second resistor coupled with the plurality of parallel p-type replica stages at a second node;

a second comparator configured to generate a second signal indicative of a comparison of a voltage at the second node with a second reference voltage; and

second logic circuitry coupled to the second comparator and to the plurality of parallel p-type replica stages, the second logic circuitry configured to determine, based on the second comparison signal, a second number (P) of the plurality of parallel p-type replica stages to approximately match the impedance of the plurality of the parallel p-type replica stages and the transmission line impedance; and

wherein the driver logic circuitry is configured to activate P of the plurality of parallel p -type driver stages.

12. The circuit of claim 11 ,

wherein the differential driver is coupled to a voltage source and to a ground;

wherein the first reference voltage is a first percentage of the voltage source;

wherein the first resistor has a predetermined resistance;

wherein the first percentage of the voltage source and the predetermined resistance are predetermined such that the first signal indicative of a comparison of a voltage at the first node with a first reference voltage reflects a comparison of the impedance of the plurality of the parallel n-type replica stages and the transmission line impedance;

wherein the second reference voltage is a second percentage of the voltage source;

wherein the second resistor has the predetermined resistance; and

wherein the second percentage of the voltage source and the predetermined resistance are predetermined such that the second signal indicative of a comparison of a voltage at the second node with a second reference voltage reflects a comparison of the impedance of the plurality of the parallel p-type replica stages and the transmission line impedance.

13. The circuit of claim 12 , wherein the first reference voltage is about twenty-five percent of the voltage source and the second reference voltage is about seventy-five percent of the voltage source.

14. The circuit of claim 11 , wherein the first calibration logic circuitry comprises a finite state machine configured to count N up, to count N down, or to hold N constant based on the first signal indicative of a comparison of a voltage at the first node with a first reference voltage; and

wherein the second calibration logic circuitry comprises a finite state machine configured to count P up, to count P down, or to hold P constant based on the second signal indicative of a comparison of a voltage at the second node with a second reference voltage.

15. The circuit of claim 11 , wherein each n-type driver stage comprises an NMOS transistor; and

each p-type driver stage comprises a PMOS transistor in parallel with an NMOS transistor.