System architecture with secure data exchange
View Patent ↗In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.
1. A system comprising:
a first bus;
a second bus;
a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a first command from the first bus and to generate a random number in response to the first command;
a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate a peripheral-to-peripheral transfer of the random number from the first peripheral to the second peripheral over the second bus such that access to the random number through the first bus is prevented, the second peripheral configured to generate a cypher key using the random number; and
a corruption detection module directly coupled to the first bus and the second bus and configured to detect data corruption in the cypher key on the second bus and to transmit a signal or message over the first bus to inform an application on the first bus of the data corruption.
2. The system of claim 1 , wherein the first peripheral is configured to:
generate integrity data; and
transfer the random number with the integrity data to the second peripheral over the second bus.
3. The system of claim 2 , wherein the first peripheral is further configured to:
transfer the random number, interleaved with the integrity data, over the second bus.
4. The system of claim 2 , wherein the first peripheral is further configured to:
transfer the random number over the second bus; and
following the transfer of the random number over the second bus, transfer the integrity data over the second bus.
5. The system of claim 2 , wherein the first peripheral is further configured to:
transfer the random number, randomly interleaved with the integrity data, over the second bus.
6. The system of claim 2 , wherein the integrity data includes a cyclic redundancy check (CRC) code.
7. The system of claim 1 , wherein the second bus is a synchronous bus.
8. A method comprising:
sending, by a master or peripheral in a system having a first bus and a second bus, a first command to a first peripheral coupled to the first bus and the second bus, the second bus configured to prevent access through the first bus to data transferred on the second bus;
receiving, by the first peripheral, the first command from the first bus;
generating, by the first peripheral, a random number in response to the first command;
initiating, by a second peripheral coupled to the second bus, a peripheral-to-peripheral transfer of the random number on the second bus from the first peripheral to the second peripheral, the second peripheral configured to generate a cypher key using the random number;
detecting, by a corruption detection module directly coupled to the first bus and the second bus, corruption in the cypher key on the second bus; and
transmitting, by the corruption detection module, a signal or message over the first bus to inform an application on the first bus of the corruption.
9. The method of claim 8 , further comprising:
generating, by the first peripheral, integrity data corresponding to the random number; and
transferring, by the first peripheral, the random number with the integrity data to the second peripheral over the second bus.
10. The method of claim 9 , further comprising:
transferring, by the first peripheral, the random number, interleaved with the integrity data, over the second bus.
11. The method of claim 9 , further comprising:
following the transfer of the random number over the second bus, transferring the integrity data over the second bus.
12. The method of claim 9 , further comprising:
transferring the random number, randomly interleaved with the integrity data, over the second bus.
13. The method of claim 9 , wherein the integrity data includes a cyclic redundancy check (CRC) code.
14. The method of claim 8 , wherein the second bus is a synchronous bus.
15. A device comprising:
an interface configured to couple to a first bus;
a second bus;
a first peripheral coupled to the interface and the second bus, the first peripheral configured to receive a command over the interface, to generate a random number in response to the command and to initiate a peripheral-to-peripheral transfer of the random number to a second peripheral over the second bus such that access to the random number through the first bus is prevented, the second peripheral configured to generate a cypher key using the random number; and
a corruption detection module directly coupled to the first bus and the second bus and configured to detect data corruption in the cypher key on the second bus and to transmit a signal or message over the first bus to inform an application on the first bus of the data corruption.
16. The device of claim 15 , wherein the second peripheral is further configured to:
generate integrity data; and
initiate transfer of the random number from the first peripheral to the second peripheral over the second bus with the integrity data.