Inter-process signaling system and method
An inter-process signaling system and method support implementation of semaphores or messaging signals between masters in a multi-master system, or between tasks in a single master system. A semaphore flag register contains one or more bits indicating whether resources are free or busy. The register is aliased to allow atomic read-and-clear of individual bits in the register. Masters poll the status of a resource until the resource reads as free. Alternatively, interrupts or events per master can be implemented to indicate availability of a resource.
1. An inter-process signaling system comprising:
a plurality of masters;
a plurality of resources shared by the plurality of masters; and
an inter-process signal module coupled to the plurality of masters and the plurality of resources, the inter-process signal module including:
a semaphore flag (SFLAG) register containing at least one bit per resource that indicates whether a resource is free or busy;
an SFLAG set (SFLAGSET) register for selectively setting individual bits in the SFLAG register; and
an SFLAG clear (SFLAGCLR) register for selectively clearing individual bits in the SFLAG register.
2. The system of claim 1 , wherein the bits in the SFLAG register are aliased to sequential memory locations, so that the bits can be accessed individually by a SFLAGCLRR register.
3. The system of claim 2 , wherein the SFLAGCLRR register provides atomic read-to-clear access.
4. The system of claim 1 , further comprising:
a plurality of semaphore mask (SMASK) registers, wherein each of the SMASK registers is associated with one of the plurality of masters and indicates which of the SFLAG register bits will produce an interrupt request for its associated master.
5. The system of claim 4 , further comprising:
an interrupt generator for generating an interrupt request based on contents of one of the SMASK registers and the SFLAG register.
6. The system of claim 4 , where an interrupt irq k is produced by
irq k =∥( S MASK[ k ]& S FLAG),
where k is positive integer value that is equal to the number of masters in the system.
7. The system of claim 1 , further comprising:
an event system coupled to the inter-process signal module, wherein the inter-process signal module is operable to produce an event output for the event system.
8. The system of claim 1 , wherein at least one of the plurality of resources is shared system memory and at least two of the plurality of masters are central processing units.
9. The system of claim 1 , further comprising:
a plurality of cross-trigger interfaces coupled to the plurality of masters and the inter-process signal module and operable to generate interrupts in response to receiving inter-process signals.
10. The system of claim 1 , wherein the inter-process signal module is operable to provide inter-process signal communication between one or more processes or threads running on a single master or multiple masters using synchronization primitives.
11. An inter-process signaling method comprising:
receiving, by an inter-process signal module, a first request from a first master to access one of a plurality of resources, wherein each resource is represented by one or more bits contained in a semaphore flag (SFLAG) register;
responsive to receiving the first request, selectively setting or clearing a bit in the SFLAG register by selectively setting or clearing a corresponding bit in one or more alias registers;
receiving, by the inter-process signal module, a second request from a second master to access one of the plurality of resources; and
sending, by the inter-process signal module to the second master, a signal indicating a current status of the requested resource.
12. The method of claim 11 , wherein individual bits of the SFLAG register are set by an SFLAG set (SFLAGSET) alias register and individual bits of the SFLAG register are cleared by an SFLAG clear (SFLAGCLR) alias register.
13. The method of claim 12 , wherein the bits in the SFLAG register are aliased to sequential memory locations, so that the bits can be accessed individually by a SFLAGCLRR register.
14. The method of claim 13 , wherein the SFLAGCLRR register provides atomic read-to-clear access.
15. The method of claim 14 , further comprising:
generating an interrupt request based on contents of one of a plurality of semaphore mask (SMASK) registers and the SFLAG register.
16. The method of claim 15 , where an interrupt irq k is produced by
irq k =∥( S MASK[ k ]& S FLAG),
where k is positive integer value that is equal to the number of masters in the system.
17. The method of claim 11 , further comprising:
producing an event output for an event system coupled to the inter-process signal module.
18. The method of claim 11 , wherein at least one of the plurality of resources is shared system memory and at least two of the plurality of masters are central processing units.
19. The method of claim 11 , further comprising:
generating interrupts in response to receiving inter-process signals from one or more masters.
20. The method of claim 11 , further comprising:
providing inter-process signal communication between one or more processes or threads using synchronization primitives.