IP Library Granted Patent US 10,809,843
Granted Patent B2
US 10,809,843 · App. 15/355,544 · Granted Oct 20, 2020

Touch sensor signal integration

Inventors: Grahame Reynolds (Southampton, GB); Hammad Syed (Southampton, GB)
Assignee: Atmel Corporation
G06F3/0416G02F1/13338G02F1/134309G06F3/044G06F3/0412G06F3/0418G02F1/13439G06F2203/04108G06F2203/04111
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Quick Facts
Patent No.
US 10,809,843
App. No.
15/355,544
Granted
Oct 20, 2020
Kind
B2
Abstract

In certain embodiments, a method includes performing a first positive integration by sensing a first rising edge of a charging signal of a touch sensor during a first synchronization period and performing a first negative integration by sensing a first falling edge of the charging signal during a second synchronization period. The method also includes toggling the charging signal, resulting in a second rising edge of the charging signal during the second synchronization period. The method further includes performing a second negative integration by sensing a second falling edge of the charging signal during a third synchronization period and performing a second positive integration by sensing a third rising edge of the charging signal during a fourth synchronization period. The first integrations are associated with a first sample measurement and the second integrations are associated with a second sample measurement.

Claims (80)

1. A device, comprising:

a touch sensor comprising a plurality of electrodes; and

a controller coupled to the touch sensor, the controller comprising logic configured, when executed, to cause the controller to:

perform a first positive integration by sensing a first rising edge of a charging signal associated with an electrode of the plurality of electrodes during a first synchronization period;

perform a first negative integration by sensing a first falling edge of the charging signal associated with the electrode of the plurality of electrodes during a second synchronization period, wherein the first positive integration and the first negative integration are associated with a first sample measurement;

toggle the charging signal, resulting in a second rising edge of the charging signal during the second synchronization period;

perform a second negative integration by sensing a second falling edge of the charging signal associated with the electrode of the plurality of electrodes during a third synchronization period; and

perform a second positive integration by sensing a third rising edge of the charging signal associated with the electrode of the plurality of electrodes during a fourth synchronization period, wherein the second negative integration and the second positive integration are associated with a second sample measurement;

wherein the first, second, third, and fourth synchronization periods occur consecutively.

2. The device of claim 1 , wherein:

the first and third synchronization periods are associated with a first type of noise;

the second and fourth synchronization periods are associated with a second type of noise; and

the summation of the first and second sample measurements cancel out the first type of noise and the second type of noise within the four synchronization periods.

3. The device of claim 1 , wherein the logic is further configured, when executed, to cause the controller to:

perform a third negative integration by sensing a third falling edge of the charging signal associated with a second electrode of the plurality of electrodes during a fifth synchronization period;

perform a third positive integration by sensing a fourth rising edge of the charging signal associated with the second electrode of the plurality of electrodes during a sixth synchronization period, wherein the third negative integration and the third positive integration are associated with a third sample measurement;

toggle the charging signal, resulting in a fourth falling edge of the charging signal during the sixth synchronization period;

perform a fourth positive integration by sensing a fifth rising edge of the charging signal associated with the second electrode of the plurality of electrodes during a seventh synchronization period; and

perform a fourth negative integration by sensing a fifth falling edge of a charging signal associated with the second electrode of the plurality of electrodes during an eighth synchronization period, wherein the fourth positive integration and the fourth negative integration are associated with a fourth sample measurement.

4. The device of claim 3 , wherein:

the first and fifth synchronization periods represent a first type of noise;

the second and sixth synchronization periods represent a second type of noise;

the third and seventh synchronization periods represent a third type of noise;

the fourth and eighth synchronization periods represent a fourth type of noise; and

a summation of the first, second, third, and fourth sample measurements cancel out the first, second, third, and fourth types of noise within the eight synchronization periods.

5. The device of claim 1 , wherein the device comprises a hybrid in-cell liquid crystal display (“LCD”), the LCD comprising one from a set of:

a checkerboard dot inverse pattern that produces a first and second type of noise; and

a checkerboard double dot inverse pattern that produces a first, second, third, and fourth type of noise.

6. The device of claim 1 , wherein the electrode of the plurality of electrodes comprises two or more electrically coupled electrodes that are positioned horizontally underneath adjacent pixel rows of a display of the device.

7. One or more computer-readable non-transitory storage media embodying logic that is operable when executed to:

perform a first positive integration by sensing a first rising edge of a charging signal associated with an electrode of a plurality of electrodes of a touch sensor during a first synchronization period;

perform a first negative integration by sensing a first falling edge of the charging signal associated with the electrode of the plurality of electrodes during a second synchronization period, wherein the first positive integration and the first negative integration are associated with a first sample measurement;

toggle the charging signal, resulting in a second rising edge of the charging signal during the second synchronization period;

perform a second negative integration by sensing a second falling edge of the charging signal associated with the electrode of the plurality of electrodes during a third synchronization period; and

perform a second positive integration by sensing a third rising edge of the charging signal associated with the electrode of the plurality of electrodes during a fourth synchronization period, wherein the second negative integration and the second positive integration are associated with a second sample measurement;

wherein the first, second, third, and fourth synchronization periods occur consecutively.

8. The media of claim 7 , wherein:

the first and third synchronization periods are associated with a first type of noise;

the second and fourth synchronization periods are associated with a second type of noise; and

the summation of the first and second sample measurements cancel out the first type of noise and the second type of noise within the four synchronization periods.

9. The media of claim 7 , wherein the logic is further operable when executed to:

perform a third negative integration by sensing a third falling edge of the charging signal associated with a second electrode of the plurality of electrodes during a fifth synchronization period;

perform a third positive integration by sensing a fourth rising edge of the charging signal associated with the second electrode of the plurality of electrodes during a sixth synchronization period, wherein the third negative integration and the third positive integration are associated with a third sample measurement;

toggle the charging signal, resulting in a fourth falling edge of the charging signal during the sixth synchronization period;

perform a fourth positive integration by sensing a fifth rising edge of the charging signal associated with the second electrode of the plurality of electrodes during a seventh synchronization period; and

perform a fourth negative integration by sensing a fifth falling edge of a charging signal associated with the second electrode of the plurality of electrodes during an eighth synchronization period, wherein the fourth positive integration and the fourth negative integration are associated with a fourth sample measurement.

10. The media of claim 9 , wherein:

the first and fifth synchronization periods represent a first type of noise;

the second and sixth synchronization periods represent a second type of noise;

the third and seventh synchronization periods represent a third type of noise;

the fourth and eighth synchronization periods represent a fourth type of noise; and

a summation of the first, second, third, and fourth sample measurements cancel out the first, second, third, and fourth types of noise within the eight synchronization periods.

11. The media of claim 7 , wherein the touch sensor is associated with a hybrid in-cell liquid crystal display (“LCD”), the LCD comprising one from a set of:

a checkerboard dot inverse pattern that produces a first and second type of noise; and

a checkerboard double dot inverse pattern that produces a first, second, third, and fourth type of noise.

12. The media of claim 7 , wherein the electrode of the plurality of electrodes comprises two or more electrically coupled electrodes that are positioned horizontally underneath adjacent pixel rows of a display of a device.

13. A method, comprising:

performing a first positive integration by sensing a first rising edge of a charging signal associated with an electrode of a plurality of electrodes of a touch sensor during a first synchronization period;

performing a first negative integration by sensing a first falling edge of the charging signal associated with the electrode of the plurality of electrodes during a second synchronization period, wherein the first positive integration and the first negative integration are associated with a first sample measurement;

toggling the charging signal, resulting in a second rising edge of the charging signal during the second synchronization period;

performing a second negative integration by sensing a second falling edge of the charging signal associated with the electrode of the plurality of electrodes during a third synchronization period; and

performing a second positive integration by sensing a third rising edge of the charging signal associated with the electrode of the plurality of electrodes during a fourth synchronization period, wherein the second negative integration and the second positive integration are associated with a second sample measurement;

wherein the first, second, third, and fourth synchronization periods occur consecutively.

14. The method of claim 13 , wherein:

the first and third synchronization periods are associated with a first type of noise;

the second and fourth synchronization periods are associated with a second type of noise; and

the summation of the first and second sample measurements cancel out the first type of noise and the second type of noise within the four synchronization periods.

15. The method of claim 13 , further comprising:

performing a third negative integration by sensing a third falling edge of the charging signal associated with the electrode of the plurality of electrodes during a fifth synchronization period;

performing a third positive integration by sensing a fourth rising edge of the charging signal associated with the electrode of the plurality of electrodes during a sixth synchronization period, wherein the third negative integration and the third positive integration are associated with a third sample measurement;

toggling the charging signal, resulting in a fourth falling edge of the charging signal during the sixth synchronization period;

performing a fourth positive integration by sensing a fifth rising edge of the charging signal associated with the electrode of the plurality of electrodes during a seventh synchronization period; and

performing a fourth negative integration by sensing a fifth falling edge of a charging signal associated with the electrode of the plurality of electrodes during an eighth synchronization period, wherein the fourth positive integration and the fourth negative integration are associated with a fourth sample measurement.

16. The method of claim 15 , wherein:

the first and fifth synchronization periods represent a first type of noise;

the second and sixth synchronization periods represent a second type of noise;

the third and seventh synchronization periods represent a third type of noise;

the fourth and eighth synchronization periods represent a fourth type of noise; and

a summation of the first, second, third, and fourth sample measurements cancel out the first, second, third, and fourth types of noise within the eight synchronization periods.

17. The method of claim 13 , wherein the electrode of the plurality of electrodes comprises two or more electrically coupled electrodes that are positioned horizontally underneath adjacent pixel rows of a display of a device.

Assignments (22)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059357/0823 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059264/0384 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 058214/0380 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0238 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2017
From: ATMEL TECHNOLOGIES U.K. LIMITED
To: ATMEL CORPORATION
Reel/Frame 041423/0507 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2016
From: REYNOLDS, GRAHAME; SYED, HAMMAD
To: ATMEL TECHNOLOGIES U.K. LIMITED
Reel/Frame 040369/0038 →
Continuity (1)
Related Publication 20180143727A1 · May 24, 2018