Dynamic programming of advanced nanometer flash memory
An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.
1. A programming circuit for use in a memory device, comprising:
a plurality of current mirrors;
a bit line coupled to a plurality of memory cells and to a set of switches, each of the switches in the set of switches coupled to one of the plurality of current mirrors;
a controller configured to control the set of switches during a programming operation of one of the plurality of memory cells, wherein each of the switches in the set of switches is turned on and turned off during at least part of the programming operation.
2. The circuit of claim 1 , wherein the set of switches comprises two switches.
3. The circuit of claim 1 , wherein the set of switches comprises four switches.
4. The circuit of claim 1 , wherein the set of switches comprises eight switches.
5. The circuit of claim 1 , wherein during the programming operation the switches in the set of switches are turned on and off sequentially.
6. The circuit of claim 3 , wherein two or more switches of the set of switches are on at the same time during at least part of the programming operation.
7. The circuit of claim 1 , wherein the controller causes an average of currents through each of the plurality of current mirrors to be provided to the bit line during the programming operation.
8. The circuit of claim 1 , wherein the memory cells are flash memory cells.
9. A method of programming a memory device comprising a plurality of current mirrors, a bit line coupled to a plurality of memory cells and to a set of switches, each of the switches in the set of switches coupled to one of the plurality of current mirrors, and a controller configured to control the set of switches during a programming operation of one of the plurality of memory cells, the method comprising:
turning on and off, by the controller during the programming operation, each switch in the set of switches in sequence.
10. The method of claim 9 , wherein the set of switches comprises two switches.
11. The method of claim 9 , wherein the set of switches comprises four switches.
12. The method of claim 9 , wherein the set of switches comprises eight switches.
13. The method of claim 9 , wherein two or more switches of the set of switches are on at the same time during at least part of the programming operation.
14. The method of claim 13 , wherein during the programming operation, the controller causes an average of currents through each of the plurality of current mirrors to be provided to the bit line.
15. The method of claim 9 , wherein the memory cells are flash memory cells.