High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks
An artificial neural network device that utilizes analog neuromorphic memory that comprises one or more non-volatile memory arrays. The embodiments comprise improved mechanisms and algorithms for tuning the non-volatile memory arrays such that the floating gates of the memory cells can be quickly and accurately injected with the desired amount of charge to signify an analog value utilized as a weight by the artificial neural network.
1. A method for tuning a plurality of non-volatile analog neuromorphic memory cells, comprising:
erasing the plurality of non-volatile analog neuromorphic cells; and
performing a tuning algorithm on each of the plurality of non-volatile analog neuromorphic memory cells, the tuning algorithm comprising:
determining a first current threshold for the cell, wherein the first current threshold is related to a desired weight level to be stored in the cell;
determining a second current threshold, wherein the second current threshold is equal to the first current threshold minus an offset value;
performing a coarse programming sequence on the cell, comprising:
performing a coarse programming operation on the cell by applying a coarse programming voltage to a terminal of the cell; and
repeating the coarse programming operation until the current through the cell during a read operation exceeds the second current threshold, wherein each time the programming operation is repeated the coarse programming voltage is increased by a predetermined coarse increment; and
performing a fine programming sequence on the cell, comprising:
performing a fine programming operation on the cell by applying a fine programming voltage to a terminal of the cell, wherein the fine programming voltage is equal to the last coarse programming voltage applied minus an offset; and
repeating the fine programming operation until the current through the cell during a read operation exceeds the first current threshold, wherein each time the fine programming operation is repeated the fine programming voltage is increased by a predetermined fine increment, wherein each predetermined fine increment is smaller than each predetermined coarse increment.
2. The method of claim 1 , further comprising:
performing a second fine programming sequence on the cell, comprising;
performing a second fine programming operation on the cell by applying a second fine programming voltage to a terminal of the cell, wherein the second fine programming voltage is equal to the last fine programming voltage applied minus an offset;
repeating the second fine programming operation until the current through the cell during a read operation exceeds the first current threshold, wherein each time the second fine programming operation is repeated the second fine programming voltage is increased by a predetermined second fine increment, wherein each predetermined second fine increment is smaller than each predetermined fine increment.
3. The method of claim 1 , wherein the predetermined coarse increments are binary search steps.
4. The method of claim 1 , wherein the predetermined coarse increments are uniform steps.
5. The method of claim 1 , wherein the pulse width of the coarse programming is larger than the pulse width of the fine programming.
6. The method of claim 1 , wherein the programming includes fixed pulse width programming.
7. The method of claim 1 , wherein the memory cell is a split 2-gate flash memory cell.
8. The method of claim 1 , wherein the memory cell is a split 3-gate flash memory cell.
9. The method of claim 1 , wherein the memory cell is a split 4-gate flash memory cell.
10. The method of claim 1 , wherein the memory cell operates in a subthreshold region.