IP Library Granted Patent US 10,819,101
Granted Patent B2
US 10,819,101 · App. 15/866,508 · Granted Oct 27, 2020

Over-current protection apparatus and method

Inventors: Pierre Irissou (Sunnyvale, CA); Etienne Colmet-Daage (Los Altos, CA)
Assignee: Microsemi Corporation
H02H5/04H02H3/06H02H3/066H02H3/085H02H3/305H02H5/048H02H9/025H04M2201/80
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Quick Facts
Patent No.
US 10,819,101
App. No.
15/866,508
Granted
Oct 27, 2020
Kind
B2
Abstract

An over-current protection apparatus constituted of: a transistor disposed on a substrate; a first thermal sense device arranged to sense a temperature reflective of a junction temperature of the transistor; a second thermal sense device arranged to sense a temperature reflective of a temperature of a casing surrounding the substrate; and a control circuitry, arranged to alternately: responsive to the sensed temperature by the first thermal sense device and the sensed temperature of the second thermal sense device being indicative that the temperature difference between the transistor junction and the substrate casing is greater than a predetermined value, switch off the transistor; and responsive to the sensed temperature by the first thermal sense device and the sensed temperature by the second thermal sense device being indicative that the temperature difference between the transistor junction and the substrate casing is not greater than the predetermined value, switch on the transistor.

Claims (31)

1. An over-current protection apparatus comprising:

a transistor disposed on a first substrate;

a first thermal sense device arranged to sense a temperature reflective of a junction temperature of said transistor;

a second thermal sense device arranged to sense a temperature reflective of a temperature of a casing surrounding said first substrate; and

a control circuitry, wherein said control circuitry is arranged, to:

responsive to said sensed temperature by said first thermal sense device and said sensed temperature of said second thermal sense device being indicative that the temperature difference between said transistor junction and the first substrate casing is greater than a predetermined value, switch said transistor to an off state;

maintain said transistor in the off state after the temperature difference between said transistor junction and the first substrate casing is no longer greater than said predetermined value; and

after a predetermined delay time and responsive to said sensed temperature by said first thermal sense device and said sensed temperature by said second thermal sense device being indicative that the temperature difference between said transistor junction and the first substrate casing is not greater than said predetermined value, switch said transistor to an on state.

2. The apparatus of claim 1 , wherein said control circuitry comprises a latch, said switch of said transistor to the off state responsive to said latch, and wherein said latch is arranged to maintain said transistor in the off state after the temperature difference between said transistor junction and the first substrate casing is no longer greater than said predetermined value.

3. The apparatus of claim 1 , wherein said first thermal sense device is positioned within said transistor.

4. The apparatus of claim 1 , wherein said first thermal sense device is positioned on said first substrate and said second thermal sense device is positioned on a second substrate, said second substrate different than said first substrate.

5. The apparatus of claim 1 , wherein said first thermal sense device and said second thermal sense device form an unbalanced current mirror,

wherein the difference between the magnitude of a current at a first side of said unbalanced current mirror and the magnitude of a current at a second side of said unbalanced current mirror is a predetermined function of said temperature difference, and

wherein said switching of said transistor is responsive to one of said first side current and said second side current.

6. An over-current protection method, the method comprising:

sensing a temperature reflective of a junction temperature of a transistor disposed on a first substrate;

sensing a temperature reflective of a temperature of a casing surrounding the first substrate;

responsive to said sensing of said junction temperature and said sensing of said casing temperature being indicative that the temperature difference between the transistor junction and the first substrate casing is greater than a predetermined value, switching the transistor to an off state;

maintaining the transistor in the off state after the temperature difference between the transistor junction and the first substrate casing is no longer greater than said predetermined value; and

after a predetermined delay time and responsive to said sensing of said junction temperature and said sensing of said casing temperature being indicative that the temperature difference between the transistor junction and the first substrate casing is not greater than said predetermined value, switching the transistor to an on state.

7. The method of claim 6 , further comprising switching on a latch, said switching the transistor to the off state is responsive to said switching on of the latch, wherein the latch is arranged, in said on state, to maintain the transistor in the off state after the temperature difference between the transistor junction and the first substrate casing is no longer greater than said predetermined value.

8. The method of claim 6 , wherein said sensing of said temperature reflective of the transistor junction temperature comprises sensing the temperature within the transistor.

9. The method of claim 6 , wherein said sensing of said temperature reflective of the first substrate casing temperature comprises sensing a temperature on a second substrate, the second substrate different than the first substrate.

10. The method of claim 6 , further comprising:

generating a first current, said generated first current output at a first side of an unbalanced current mirror; and

generating a second current, said generated second current output as a second side of the imbalance current mirror, the difference between the magnitude of said generated second current and the magnitude of said generated first current is a predetermined function of said temperature difference,

wherein said switching of the transistor to the on state and to the off state is responsive to one of said generated first current and said generated second current.

11. The apparatus of claim 1 , where said transistor is coupled to a load and wherein the temperature difference between said transistor junction and the first substrate casing being greater than the predetermined value is indicative of a short circuit along a current path of the load.

12. The apparatus of claim 1 , wherein said first thermal sense device and said second thermal sense device form an unbalanced current mirror and wherein an emitter area of said second thermal sense device is twice the size of an emitter area of said first thermal sense device.

13. The method of claim 6 , where said transistor is coupled to a load and wherein the temperature difference between said transistor junction and the first substrate casing being greater than the predetermined value is indicative of a short circuit along a current path of the load.

14. The apparatus of claim 6 , wherein said first thermal sense device and said second thermal sense device form an unbalanced current mirror and wherein an emitter area of said second thermal sense device is twice the size of an emitter area of said first thermal sense device.

Assignments (18)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059357/0823 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059264/0384 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0238 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 058214/0380 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2018
From: IRISSOU, PIERRE; COLMET-DAAGE, ETIENNE
To: MICROSEMI CORPORATION
Reel/Frame 044779/0470 →