Method to form a 3D integrated circuit
A method to form a 3D integrated circuit, the method including: providing a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; providing a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; and then performing a face-to-face bonding of the second wafer on top of the first wafer, where the face-to-face bonding includes copper to copper bonding; and thinning the second crystalline substrate to a thickness of less than 5 micro-meters.
1. A method to form a 3D integrated circuit, the method comprising:
providing a first wafer comprising a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers,
wherein said first copper interconnecting layers at least interconnect said plurality of first transistors;
providing a second wafer comprising a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers,
wherein said second copper interconnecting layers at least interconnect said plurality of second transistors; and then
performing a face-to-face bonding of said second wafer on top of said first wafer,
wherein said face-to-face bonding comprises copper to copper bonding; and
thinning said second crystalline substrate to a thickness of less than 5 micro-meters.
2. The method of claim 1 , further comprising:
forming a via through said thinned said second crystalline substrate,
wherein said via has a radius of less than 1 micro-meter.
3. The method of claim 1 ,
wherein said second crystalline substrate does not comprise a built-in oxide layer.
4. The method of claim 1 ,
wherein said face-to-face bonding comprises hybrid bonding.
5. The method of claim 1 ,
wherein said first wafer comprises memory control circuits and said second wafer comprises a plurality of memory cells, or, said second wafer comprises memory control circuits and said first wafer comprises a plurality of memory cells.
6. The method of claim 1 , further comprising:
forming vias through said thinned said second crystalline substrate,
wherein said vias have a radius of less than 1 micro-meter; and
wherein at least one of said vias is used to connect said 3D integrated circuit to an external device.
7. The method of claim 1 ,
wherein said first wafer comprises a plurality of self-aligned memory levels.
8. A method to form a 3D integrated circuit, the method comprising:
providing a first wafer comprising a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers,
wherein said first copper interconnecting layers at least interconnect said plurality of first transistors;
providing a second wafer comprising a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers,
wherein said second copper interconnecting layers at least interconnect said plurality of second transistors; and then
performing a face-to-face bonding of said second wafer on top of said first wafer,
wherein said face-to-face bonding comprises metal to metal bonding,
wherein said first wafer comprises memory control circuits and said second wafer comprises a plurality of memory cells, or said second wafer comprises memory control circuits and said first wafer comprises a plurality of memory cells.
9. The method of claim 8 ,
wherein said second crystalline substrate is thinned to a thickness of less than 5 micro-meters.
10. The method of claim 8 ,
wherein said second crystalline substrate does not comprise a built-in oxide layer.
11. The method of claim 8 ,
wherein said face-to-face bonding comprises hybrid bonding.
12. The method of claim 8 ,
wherein processing of at least one of said plurality of second transistors comprises a gate replacement step.
13. The method of claim 8 , further comprising:
forming vias through said second crystalline substrate,
wherein at least one of said vias is used to connect said 3D integrated circuit to an external device.
14. The method of claim 8 ,
wherein said first wafer comprises a plurality of self-aligned memory levels.
15. A method to form a 3D integrated circuit, the method comprising:
providing a first wafer comprising a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers,
wherein said first copper interconnecting layers at least interconnect said plurality of first transistors;
providing a second wafer comprising a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers,
wherein said second copper interconnecting layers at least interconnect said plurality of second transistors; and then
performing a face-to-face bonding of said second wafer on top of said first wafer,
wherein said face-to-face bonding comprises copper to copper bonding; and
thinning said second crystalline substrate to a thickness of less than 20 micro-meters.
16. The method of claim 15 ,
wherein said second crystalline substrate does not comprise a built-in oxide layer.
17. The method of claim 15 ,
wherein said face-to-face bonding comprises hybrid bonding.
18. The method of claim 15 ,
wherein said first wafer comprises memory control circuits and said second wafer comprises a plurality of memory cells, or said second wafer comprises memory control circuits and said first wafer comprises a plurality of memory cells.
19. The method of claim 15 , further comprising:
forming vias through said thinned said second crystalline substrate, and
wherein at least one of said vias is used to connect said 3D integrated circuit to an external device.
20. The method of claim 15 ,
wherein said first wafer comprises a plurality of self-aligned memory levels.