3D integrated circuit device and structure with hybrid bonding
A 3D integrated circuit, the circuit including: a first level including a first wafer, the first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second level including a second wafer, the second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors, where the second level is bonded to the first level, where the bonded includes metal to metal bonding, where the bonded includes oxide to oxide bonding, and where at least one of the second transistors include a replacement gate.
1. A 3D semiconductor integrated circuit, the circuit comprising:
a first level comprising a first wafer, said first wafer comprising a first crystalline substrate, a plurality of first transistors, and a plurality of first copper interconnecting layers,
wherein said first copper interconnecting layers at least interconnect said plurality of first transistors;
a second level comprising a second wafer, said second wafer comprising a second crystalline substrate, a plurality of second transistors, and a plurality of second copper interconnecting layers,
wherein said plurality of second copper interconnecting layers at least interconnect said plurality of second transistors,
wherein said second level is hybrid bonded to said first level,
wherein said hybrid bonded comprises metal to metal bonding,
wherein said hybrid bonded additionally comprises oxide to oxide bonding disposed on a same level as the metal to metal bonding; and
a first metal layer, a second metal layer, and a third metal layer,
wherein said first metal layer, said second metal layer, and said third metal layer are disposed between said first crystalline substrate and said second crystalline substrate,
wherein said second metal layer is disposed between said first metal layer and said third metal layer,
wherein said second metal layer thickness is at least double that of said first metal layer thickness, and
wherein said second metal layer thickness is at least double that of said third metal layer thickness.
2. The 3D integrated circuit of claim 1 ,
wherein said plurality of second transistors comprises at least two side gates.
3. The 3D integrated circuit of claim 1 ,
wherein at least one of said plurality of second transistors comprises a replacement gate comprising a High-k Metal Gate (HKMG) disposed atop a High-k oxide dielectric layer.
4. The 3D integrated circuit of claim 1 ,
wherein said second level comprises a DRAM memory array.
5. The 3D integrated circuit of claim 1 ,
wherein said first level comprises memory control circuits, and
wherein said second level comprises a plurality of memory cells.
6. The 3D integrated circuit of claim 1 , further comprising:
vias through said second crystalline substrate,
wherein at least one of said vias connects said 3D semiconductor integrated circuit to an external device.
7. The 3D integrated circuit of claim 1 ,
wherein said second crystalline substrate thickness is less than 10 microns.
8. A 3D integrated circuit, the circuit comprising:
a first level comprising a first wafer, said first wafer comprising a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers,
wherein said first copper interconnecting layers at least interconnect said plurality of first transistors; and
a second level comprising a second wafer, said second wafer comprising a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers,
wherein said second copper interconnecting layers at least interconnect said plurality of second transistors,
wherein said second level is hybrid bonded to said first level,
wherein said hybrid bonded comprises metal to metal bonding,
wherein said hybrid bonded additionally comprises oxide to oxide bonding disposed on a same level as the metal to metal bonding, and
wherein at least one of said plurality of second transistors comprises a replacement gate comprising a High-k Metal Gate (HKMG) disposed atop a High-k oxide dielectric layer.
9. The 3D integrated circuit of claim 8 ,
wherein said plurality of second transistors comprises at least two side gates.
10. The 3D integrated circuit of claim 8 , further comprising:
a first metal layer, a second metal layer, and a third metal layer,
wherein said first metal layer, said second metal layer, and said third metal layer are disposed between said first crystalline substrate and said second crystalline substrate,
wherein said second metal layer is disposed between said first metal layer and said third metal layer,
wherein said second metal layer thickness is at least double that of said first metal layer thickness, and
wherein said second metal layer thickness is at least double that of said third metal layer thickness.
11. The 3D integrated circuit of claim 8 ,
wherein said second level comprises a DRAM memory array.
12. The 3D integrated circuit of claim 8 ,
wherein said first level comprises memory control circuits, and
wherein said second level comprises a plurality of memory cells.
13. The 3D integrated circuit of claim 8 , further comprising:
vias through said second crystalline substrate,
wherein at least one of said vias connects said 3D integrated circuit to an external device.
14. The 3D integrated circuit of claim 8 ,
wherein said second crystalline substrate thickness is less than 10 microns.
15. A 3D integrated circuit, the circuit comprising:
a first level comprising a first wafer, said first wafer comprising a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers,
wherein said first copper interconnecting layers at least interconnect said plurality of first transistors; and
a second level comprising a second wafer, said second wafer comprising a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers,
wherein said second copper interconnecting layers at least interconnect said plurality of second transistors,
wherein said second level is hybrid bonded to said first level,
wherein said hybrid bonded comprises metal to metal bonding,
wherein said hybrid bonded additionally comprises oxide to oxide bonding disposed on a same level as the metal to metal bonding, and
wherein said second level comprises a DRAM memory array.
16. The 3D integrated circuit of claim 15 , further comprising:
a via disposed through said second crystalline substrate,
wherein said via has a radius of less than 1 micro-meter.
17. The 3D integrated circuit of claim 15 , further comprising:
a first metal layer, a second metal layer, and a third metal layer,
wherein said first metal layer, said second metal layer, and said third metal layer are disposed between said first crystalline substrate and said second crystalline substrate,
wherein said second metal layer is disposed between said first metal layer and said third metal layer,
wherein said second metal layer thickness is at least double that of said first metal layer thickness, and
wherein said second metal layer thickness is at least double that of said third metal layer thickness.
18. The 3D integrated circuit of claim 15 ,
wherein at least one of said plurality of second transistors comprises a replacement gate comprising a High-k Metal Gate (HKMG) disposed atop a High-k oxide dielectric layer.
19. The 3D integrated circuit of claim 15 , further comprising:
vias through said second crystalline substrate,
wherein at least one of said vias connects said 3D integrated circuit to an external device.
20. The 3D integrated circuit of claim 15 ,
wherein said second crystalline substrate thickness is less than 10 microns.