Method to form a 3D semiconductor device and structure
A method to form a 3D semiconductor device, the method including: providing a first level including first circuits, the first circuits including first transistors and first interconnection; preparing a second level including a silicon layer; forming second circuits over the second level, the second circuits including second transistors and second interconnection; transferring with bonding the second level on top of the first level; and then thinning the second level to a thickness of less than thirty microns, where the bonding includes oxide to oxide bonds, where the bonding includes metal to metal bonds, and where at least one of the metal to metal bond structures has a pitch of less than 1 micron from another of the metal to metal bond structures.
1. A method to form a 3D semiconductor device, the method comprising:
providing a first level comprising first circuits, said first circuits comprising first transistors and first interconnection;
preparing a second level comprising a silicon layer;
forming second circuits over said second level, said second circuits comprising second transistors and second interconnection;
transferring with bonding said second level on top of said first level; and then
thinning said second level to a thickness of less than thirty microns,
wherein said bonding comprises oxide to oxide bonds,
wherein said bonding comprises metal to metal bonds, and
wherein at least one of said metal to metal bond structures has a pitch of less than 1 micron from another of said metal to metal bond structures.
2. The method according to claim 1 , further comprising:
performing growth of an epitaxial layer on top of said silicon layer,
wherein said epitaxial layer comprises non-silicon atoms.
3. The method according to claim 1 ,
wherein at least one of said second transistors comprises a High-k Metal Gate (“HKMG”).
4. The method according to claim 1 , further comprising:
constructing a Global Power distribution network,
wherein said Global Power distribution network distributes power to at least one Local Power distribution network.
5. The method according to claim 1 ,
wherein a first operating voltage of said first circuits differs by at least 15% from a second operating voltage of said second circuits.
6. The method according to claim 1 , further comprising:
forming connection pads at said first level bottom face,
wherein said connection pads provide connections for external devices.
7. The method according to claim 1 ,
wherein said thinning of said second level results in a final second level thickness of less than ten microns.
8. A method to form a 3D semiconductor device, the method comprising:
providing a first level comprising first circuits, said first circuits comprising first transistors and first interconnection;
preparing a second level comprising a silicon layer;
forming second circuits over said second level, said second circuits comprising second transistors and second interconnection;
transferring with bonding said second level on top of said first level; and then
thinning said second level to a thickness of less than thirty microns,
wherein said device comprises an upper most semiconductor level,
wherein said upper most semiconductor level comprises Input/Output (“I/O”) circuits designed to connect said device to external devices, and
wherein said bonding is hybrid bonding.
9. The method according to claim 8 , further comprising:
performing growth of an epitaxial layer on top of said silicon layer,
wherein said epitaxial layer comprises non-silicon atoms.
10. The method according to claim 8 ,
wherein at least one of said metal to metal bond structures have a pitch of less than 1 micron from another of said metal to metal bond structures.
11. The method according to claim 8 , further comprising:
constructing a Global Power distribution network,
wherein said Global Power distribution network distributes power to at least one Local Power distribution network.
12. The method according to claim 8 ,
wherein a first operating voltage of said first circuit differs by at least 15% from a second operating voltage of said second circuit.
13. The method according to claim 8 , further comprising:
forming connection pads at said first level bottom face,
wherein said connection pads provide connections for external devices.
14. The method according to claim 8 ,
wherein at least one of said second transistors comprises a High-k Metal Gate (“HKMG”).
15. A method to form a 3D semiconductor device, the method comprising:
providing a first level comprising first circuits, said first circuits comprising first transistors and first interconnection;
preparing a second level comprising a silicon layer;
forming second circuits over said second level, said second circuits comprising second transistors and second interconnection;
transferring with bonding said second level on top of said first level; and then
thinning said second level to a thickness of less than thirty microns; and
forming heat removal paths designed to remove heat from said second circuits to an external surface of said 3D semiconductor device,
wherein said bonding is hybrid bonding.
16. The method according to claim 15 , further comprising:
performing growth of an epitaxial layer on top of said silicon layer,
wherein said epitaxial layer comprises non-silicon atoms.
17. The method according to claim 15 ,
wherein at least one of said metal to metal bond structures have a pitch of less than 1 micron from another of said metal to metal bond structures.
18. The method according to claim 15 , further comprising:
constructing a Global Power distribution network,
wherein said Global Power distribution network distributes power to at least one Local Power distribution network.
19. The method according to claim 15 , further comprising:
forming connection pads at said first level bottom face,
wherein said connection pads provide connections for external devices.
20. The method according to claim 15 ,
wherein at least one of said second transistors comprises a High-k Metal Gate (“HKMG”).