Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

1. A semiconductor device comprising:

a porous dielectric layer including an upper recessed portion and a lower recessed portion;

a conductive layer disposed in the lower recessed portion;

a cap layer disposed on sidewalls of the upper recessed portion and covering an upper surface of the conductive layer; and

an interlayer dielectric disposed on the cap layer and filling a remainder of the upper recessed portion,

wherein an upper surface of the porous dielectric layer is substantially coplanar with an upper surface of the interlayer dielectric.

2. The semiconductor device of claim 1 , wherein the cap layer is a conformal dielectric layer.

3. The semiconductor device of claim 1 , wherein an upper surface of the upper recessed portion is wider than an upper surface of the lower recessed portion.

4. The semiconductor device of claim 3 , further comprising a fully aligned via, a lower portion of the fully aligned via disposed in a region of the upper recessed portion and contacting the conductive layer.

5. The semiconductor device of claim 1 , wherein the cap layer comprises silicon, carbon, and nitrogen.

6. A semiconductor device comprising:

a porous dielectric layer including an upper recessed portion and a lower recessed portion;

a barrier layer disposed on sidewalls and on a lower surface of the lower recessed portion;

a conductive layer disposed on the barrier layer and in the lower recessed portion, the conductive layer and opposing sidewall portions of the barrier layer each having an upper surface collectively defining an upper surface of the lower recessed portion;

a cap layer disposed on sidewalls of the upper recessed portion and covering the upper surface of the lower recessed portion; and

an interlayer dielectric filling a remainder of the upper recessed portion,

wherein an upper surface of the porous dielectric layer is substantially coplanar with an upper surface of the interlayer dielectric.

7. The semiconductor device of claim 6 , wherein the cap layer is a conformal dielectric layer.

8. The semiconductor device of claim 6 , wherein an upper surface of the upper recessed portion is wider than the upper surface of the lower recessed portion.

9. The semiconductor device of claim 8 , further comprising a fully aligned via, a lower portion of the fully aligned via disposed in a region of the upper recessed portion and contacting the conductive layer.

10. The semiconductor device of claim 6 , wherein the cap layer comprises silicon, carbon, and nitrogen.

11. A semiconductor device comprising:

a first recess within a porous dielectric layer having an upper and a lower recessed portion;

a second recess within the porous dielectric layer having an upper and a lower recessed portion;

a first metal line disposed in the lower recessed portion of the first recess;

a second metal line disposed in the lower recessed portion of the second recess, wherein the first and second metal lines are adjacent and parallel;

a first cap layer having first and second opposing sides and a bottom, disposed on the first metal line and on opposing sidewalls of the upper recessed portion of the first recess;

a second cap layer having first and second opposing sides and a bottom, disposed on the second metal line and on opposing sidewalls of the upper recessed portion of the second recess;

a first interlayer dielectric filling a remainder of the upper recessed portion of the first recess;

a second interlayer dielectric filling a remainder of the upper recessed portion of the second recess; and

a region of the porous dielectric layer between the upper recessed portion of the first recess and the upper recessed portion of the second recess having an upper surface that is substantially coplanar with an upper surface of the first and second interlayer dielectrics.

12. The semiconductor device of claim 11 , wherein each of the first cap layer and the second cap layer is a conformal dielectric layer.

13. The semiconductor device of claim 11 , further comprising:

a first barrier layer having first and second opposing sides and a bottom, disposed on opposing sidewalls and on a lower surface of the lower recessed portion of the first recess, underlying the first metal line; and

a second barrier layer having first and second opposing sides and a bottom, disposed on opposing sidewalls and on a lower surface of the lower recessed portion of the second recess, underlying the second metal line.

14. The semiconductor device of claim 13 , wherein a first combined width of:

(i) an upper surface of the first interlayer dielectric;

(ii) an upper surface of the first cap layer on a sidewall of the upper recessed portion of the first recess; and

(iii) an upper surface of the first cap layer on an opposing sidewall of the upper recessed portion of the first recess;

is wider than a second combined width of:

(i) an upper surface of the first metal line;

(ii) an upper surface of the first barrier layer on a sidewall of the lower recessed portion of the first recess; and

(iii) an upper surface of the first barrier layer on an opposing sidewall of the lower recessed portion of the first recess.

15. The semiconductor device of claim 11 , wherein a width of the upper surface of a region of the porous dielectric layer between the upper recessed portion of the first recess and the upper recessed portion of the second recess is between 3 nm to 50 nm.

16. The semiconductor device of claim 11 , wherein the first and second cap layers comprise silicon, carbon, and nitrogen.

17. A semiconductor device comprising:

a first trench within a porous dielectric layer having an upper and a lower trench portion;

a second trench within the porous dielectric layer having an upper and a lower trench portion;

a first metal line disposed in the lower trench portion of the first trench;

a second metal line disposed in the lower trench portion of the second trench, wherein the first and second metal lines are adjacent and parallel;

a first barrier layer having first and second opposing sides and a bottom, disposed on opposing sidewalls and on a lower surface of the lower trench portion of the first trench, underlying the first metal line;

a second barrier layer having first and second opposing sides and a bottom, disposed on opposing sidewalls and on a lower surface of the lower trench portion of the second trench, underlying the second metal line;

a first cap layer having first and second opposing sides and a bottom, disposed on the first metal line and on opposing sidewalls of an upper recessed portion of the first trench;

a second cap layer having first and second opposing sides and a bottom, disposed on the second metal line and on opposing sidewalls of an upper recessed portion of the second trench;

a first interlayer dielectric filling a remainder of the upper trench portion of the first trench;

a second interlayer dielectric filling a remainder of the upper trench portion of the second trench; and

a region of the porous dielectric layer between the upper trench portion of the first trench and the upper trench portion of the second trench having an upper surface that is substantially coplanar with an upper surface of the first and second interlayer dielectrics.

18. The semiconductor device of claim 17 , wherein each of the first and the second cap layer is a conformal dielectric layer.

19. The semiconductor device of claim 17 , wherein a first combined width of:

(i) an upper surface of the first interlayer dielectric;

(ii) an upper surface of the first cap layer on a sidewall of the upper recessed portion of the first trench; and

(iii) an upper surface of the first cap layer on an opposing sidewall of the upper recessed portion of the first trench;

is wider than a second combined width of:

(i) an upper surface of the first metal line;

(ii) an upper surface of the first barrier layer on a sidewall of the lower trench portion of the first trench; and

(iii) an upper surface of the first barrier layer on an opposing sidewall of the lower trench portion of the first trench.

20. The semiconductor device of claim 17 , wherein a width of the upper surface of the region of the porous dielectric layer between the upper trench portion of the first trench and the upper trench portion of the second trench is between 3 nm to 50 nm.

21. The semiconductor device of claim 17 , wherein the first and the second cap layers comprise silicon, carbon, and nitrogen.