IP Library Granted Patent US 12,660,178
Granted Patent B2
US 12,660,178 · App. 17/406,493 · Granted Jun 16, 2026

Three-dimensional memory device and method of making thereof using double pitch word line formation

Inventors: Tatsuya Hinoue (Yokkaichi, JP); Naoki Takeguchi (Nagoya, JP)
Assignee: Sandisk Technologies, Inc.
H10B43/20H10B43/10H10B43/27H10B43/35
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,660,178
App. No.
17/406,493
Granted
Jun 16, 2026
Kind
B2
Abstract

A three-dimensional memory device includes a vertical repetition of multiple instances of a unit layer stack, memory openings vertically extending through the vertical repetition, and memory opening fill structures located within the memory openings. Each of the memory opening fill structures contains a respective vertical stack of memory elements. The unit layer stack includes, from bottom to top or from top to bottom, a cavity-free insulating layer that is free of any cavity therein, a first-type electrically conductive layer, a cavity-containing insulating layer including an encapsulated cavity therein, and a second-type electrically conductive layer.

Claims (22)

1 . A three-dimensional memory device, comprising:

a vertical repetition of multiple instances of a unit layer stack, wherein the unit layer stack comprises, from bottom to top or from top to bottom, a cavity-free insulating layer that is free of any cavity therein, a first-type electrically conductive layer, a cavity-containing insulating layer including an encapsulated cavity therein, and a second-type electrically conductive layer;

a retro-stepped dielectric material portion overlying, and contacting, stepped surface of the vertical repetition;

memory openings vertically extending through the vertical repetition; and

memory opening fill structures located within the memory openings,

wherein:

each of the memory opening fill structures comprises a respective vertical stack of memory elements;

the first-type electrically conductive layers, the second-type electrically conductive layers, and the cavity-free insulating layers are free of lateral recesses and contact the retro-stepped dielectric material portion; and

the cavity-containing insulating layers comprises lateral recesses into which a dielectric material of the retro-stepped dielectric material portion laterally protrude.

2 . The three-dimensional memory device of claim 1 , wherein each of the encapsulated cavities is laterally spaced from the memory opening fill structures by tubular portions of a respective one of the cavity-containing insulating layers.

3 . The three-dimensional memory device of claim 1 , wherein each of the encapsulated cavities comprises an air gap which is free of any solid phase material.

4 . The three-dimensional memory device of claim 1 , further comprising an insulating material portion comprising a same dielectric material as the cavity-containing insulating layers and connected to each of the cavity-containing insulating layers.

5 . The three-dimensional memory device of claim 4 , wherein the insulating material portion comprises an insulating spacer laterally surrounding a backside contact via structure that vertically extends through each layer within the vertical repetition.

6 . The three-dimensional memory device of claim 5 , wherein each of the cavity-containing insulating layers comprises a respective laterally-extending seam that continuously extends from a respective one of the encapsulated cavities through the insulating spacer and to the backside contact via structure.

7 . The three-dimensional memory device of claim 4 , wherein the insulating material portion comprises a plurality of sidewalls that contact sidewalls of each of the cavity-free insulating layers, each of the first-type electrically conductive layers, and each of the second-type electrically conductive layers within the vertical repetition.

8 . A three-dimensional memory device, comprising:

a vertical repetition of multiple instances of a unit layer stack, wherein the unit layer stack comprises, from bottom to top or from top to bottom, a cavity-free insulating layer that is free of any cavity therein, a first-type electrically conductive layer, a cavity-containing insulating layer including an encapsulated cavity therein, and a second-type electrically conductive layer;

memory openings vertically extending through the vertical repetition; and

memory opening fill structures located within the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements,

wherein:

the first-type electrically conductive layers and the second-type electrically conductive layers consist essentially of a single metal; and

each of the first-type electrically conductive layers and the second-type electrically conductive layers contacts a horizontal surface of a respective one of the cavity-free insulating layers and a horizontal surface of a respective one of the cavity-containing insulating layers.

Assignments (4)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2021
From: HINOUE, TATSUYA; TAKEGUCHI, NAOKI
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 057230/0347 →
Continuity (2)
Continuation In Part 17351811 · Jun 18, 2021
Related Publication 20220406794A1 · Dec 22, 2022
References Cited (64)
US 8349681B2 · Alsmeier et al. · 2013 [cited by applicant]
US 9252151B2 · Chien et al. · 2016 [cited by applicant]
US 9576975B2 · Zhang et al. · 2017 [cited by applicant]
US 9634024B2 · Kanamori · 2017 [cited by examiner]
US 9716105B1 · Tsutsumi · 2017 [cited by applicant]
US 9748311B2 · Fantini · 2017 [cited by examiner]
US 9922987B1 · Mizutani et al. · 2018 [cited by applicant]
US 9960181B1 · Cui et al. · 2018 [cited by applicant]
US 9972640B1 · Kai et al. · 2018 [cited by applicant]
US 10083982B2 · Shigemura et al. · 2018 [cited by applicant]
US 10192784B1 · Cui et al. · 2019 [cited by applicant]
US 10256247B1 · Kanakamedala et al. · 2019 [cited by applicant]
US 10290648B1 · Zhou et al. · 2019 [cited by applicant]
US 10347654B1 · Iwai et al. · 2019 [cited by applicant]
US 10453854B2 · Kanno et al. · 2019 [cited by applicant]
US 10461163B2 · Kanakamedala et al. · 2019 [cited by applicant]
US 10608010B2 · Terasawa et al. · 2020 [cited by applicant]
US 10615172B2 · Nagata et al. · 2020 [cited by applicant]
US 10651196B1 · Sharangpani et al. · 2020 [cited by applicant]
US 10700089B1 · Hojo et al. · 2020 [cited by applicant]
US 10707233B1 · Cui et al. · 2020 [cited by applicant]
US 10818542B2 · Cui et al. · 2020 [cited by applicant]
US 10872901B2 · Yun · 2020 [cited by examiner]
US 10923498B2 · Otsu et al. · 2021 [cited by applicant]
US 20120001249A1 · Alsmeier et al. · 2012 [cited by applicant]
US 20150008505A1 · Chien et al. · 2015 [cited by applicant]
US 20150294980A1 · Lee et al. · 2015 [cited by applicant]
US 20150380431A1 · Kanamori et al. · 2015 [cited by applicant]
US 20160086972A1 · Zhang et al. · 2016 [cited by applicant]
US 20160276359A1 · Oginoe et al. · 2016 [cited by applicant]
US 20160358933A1 · Rabkin et al. · 2016 [cited by applicant]
US 20170125538A1 · Sharangpani et al. · 2017 [cited by applicant]
US 20170373079A1 · Sharangpani et al. · 2017 [cited by applicant]
US 20180033646A1 · Sharangpani et al. · 2018 [cited by applicant]
US 20180090373A1 · Sharangpani et al. · 2018 [cited by applicant]
US 20180138194A1 · Shigemura et al. · 2018 [cited by applicant]
US 20190148392A1 · Kanno et al. · 2019 [cited by applicant]
US 20190148506A1 · Kanakamedala et al. · 2019 [cited by applicant]
US 20190280001A1 · Terasawa et al. · 2019 [cited by applicant]
US 20190348435A1 · Nagata et al. · 2019 [cited by applicant]
US 20200013796A1 · Fujita · 2020 [cited by applicant]
US 20200035694A1 · Kaminaga · 2020 [cited by applicant]
US 20200411552A1 · Bin et al. · 2020 [cited by applicant]
US 20210091106A1 · Wang et al. · 2021 [cited by applicant]
CN 109326608A · 2019 [cited by applicant]
WO WO2021029916A1 · 2021 [cited by applicant]
USPTO Office Communication, Non-Final Office Action for U.S. Appl. No. 17/351,756, mailed on Feb. 11, 2025, 27 pages. [cited by applicant]
ISR—Notification of Transmittal of The International Search Report and Written Opinion of the International Searching Authority for International Patent Application No. PCT/US2022/013971, mailed Jun. 2, 2022, 17 pages. [cited by applicant]
USPTO Office Communication, Non-Final Office Communication for U.S. Appl. No. 17/351,789, mailed on Dec. 28, 2023, 32 pages. [cited by applicant]
USPTO Office Communication, Notice of Allowance and Fee(s) Due for U.S. Appl. No. 17/351,811, mailed Nov. 7, 2023, 19 pages. [cited by applicant]
Endoh et al., “Novel Ultra High Density Memory with a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36. [cited by applicant]
Akiki, G. et al., “Area selective deposition of silicon by plasma enhanced chemical vapor deposition using a fluorinated precursor,” Applied Surface Science, vol. 531, No. 147305, pp. 1-4, (2000); https://doi.org/10.101… [cited by applicant]
U.S. Appl. No. 16/916,476, filed Jun. 30, 2020, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 16/918,463, filed Jul. 1, 2020, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 16/918,493, filed Jul. 1, 2020, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 16/934,445, filed Jul. 21, 2020, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/081,458, filed Oct. 27, 2020, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/169,987, filed Feb. 8, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/189,153, filed Mar. 1, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/192,463, filed Mar. 4, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/233,799, filed Apr. 19, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/351,756, filed Jun. 18, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/351,789, filed Jun. 18, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/351,811, filed Jun. 18, 2021, SanDisk Technologies LLC. [cited by applicant]