IP Library › Granted Patent US 12,199,015
Granted Patent B2
US 12,199,015 · App. 17/574,902 · Granted Jan 14, 2025

Semiconductor device including via structure and method for manufacturing the same

Inventors: Yeonjin Lee (Suwon-si, KR); Jongmin Lee (Suwon-si, KR); Jeonil Lee (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L23/481H01L21/76898H01L25/0657H10B99/22H01L24/02H01L24/05H01L24/06H01L24/13H01L2224/0221H01L2224/02372H01L2224/05569H01L2224/0557H01L2224/05573H01L2224/06181H01L2224/13007H01L2225/06513H01L2225/06517H01L2225/06544
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Quick Facts
Patent No.
US 12,199,015
App. No.
17/574,902
Granted
Jan 14, 2025
Kind
B2
Abstract

A semiconductor device according to some example embodiments includes a substrate, an insulating structure covering the substrate, a transistor between the substrate and the insulating structure, a via insulating layer extending through the insulating structure and the substrate, a plurality of via structures extending through the via insulating layer, a plurality of conductive structures respectively connected to the plurality of via structures, and a plurality of bumps respectively connected to the conductive structures.

Claims (17)

1. A semiconductor device comprising:

a substrate;

an insulating structure covering the substrate;

a transistor between the substrate and the insulating structure;

a via insulating layer extending through the insulating structure and the substrate;

a plurality of via structures extending through the via insulating layer and surrounded by the via insulating layer;

a plurality of conductive structures respectively connected to the plurality of via structures; and

a plurality of bumps respectively connected to the conductive structures,

wherein an upper surface of the via insulating layer is arranged at a same level as an upper surface of the substrate.

2. The semiconductor device according to claim 1 , wherein a bottom surface of the via insulating layer is coplanar with a bottom surface of the insulating structure.

3. The semiconductor device according to claim 1 , wherein each of the plurality of via structures comprises a conductive layer and a barrier layer surrounding the conductive layer.

4. The semiconductor device according to claim 1 , further comprising:

a first insulating layer covering the substrate,

wherein top surfaces of the plurality of via structures are coplanar with a top surface of the first insulating layer.

5. The semiconductor device according to claim 1 , wherein,

the insulating structure comprises a second insulating layer covering the transistor, and a mask layer covering the second insulating layer, and

bottom surfaces of the plurality of via structures are coplanar with a bottom surface of the mask layer.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE SECOND INVENTORS NAME PREVIOUSLY RECORDED AT REEL: 058669 FRAME: 0907. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 9, 2022
From: LEE, YEONJIN; LEE, JONGMIN; LEE, JEONIL
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 061119/0278 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2022
From: LEE, YEONJIN; LEE, JONGMINN; LEE, JEONIL
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 058669/0907 →
Priority Claims (1)
KR 10-2021-0087703 · Jul 5, 2021 · national
Continuity (1)
Related Publication 20230005818A1 · Jan 5, 2023
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