Granted Patent B2

US 12,693,977 · App. 17/708,435 · Granted Jul 28, 2026

Inventors: Hanna Alam (Jish, IL); Yuval Bustan (Moshav Mismeret, IL); Tomer Exterman (Petach Tiqwa, IL); Dor Kahana (Ramat Gan, IL); Larisa Novakovsky (Haifa, IL); Joseph Nuzman (Haifa, IL)

Assignee: Intel Corporation

G06F12/0811G06F2212/62

Abstract

Claims (34)

1 . An apparatus comprising:

a first cache having a higher level than a second cache; and

circuitry to determine a caching policy between the first cache and the second cache based at least in part on a comparison of a number of active processor cores and a threshold value,

wherein the caching policy is one of an inclusive caching policy or a non-inclusive caching policy.

2 . The apparatus of claim 1 , wherein the circuitry is to dynamically determine the caching policy during runtime.

3 . The apparatus of claim 1 , comprising a machine learning model to determine the threshold value based on telemetry data.

4 . The apparatus of claim 3 , wherein training of the machine learning model is to be performed offline.

5 . The apparatus of claim 3 , wherein the telemetry data is to be collected during a selected period of time.

6 . The apparatus of claim 3 , wherein the machine learning model is to operate in accordance with a logistic regression model.

7 . The apparatus of claim 3 , wherein the telemetry data includes one or more of:

statistic data of a processor core, statistic data of a storage device, and telemetry data sent from a System On Chip (SOC) device.

8 . The apparatus of claim 7 , wherein the storage device comprises a cache, wherein the statistic data of the storage device includes a number of stalls, queue occupancy, and cache pre-fetcher data.

9 . The apparatus of claim 1 , wherein the first cache comprises one or more of a Last Level Cache and a Level 3 (L3) cache.

10 . The apparatus of claim 1 , wherein the second cache comprises one or more of a Mid-Level Cache (MLC) and Level 2 (2) cache.

11 . The apparatus of claim 1 , wherein the inclusive caching policy is to ensure that any cache line present in the second cache is also present in the first cache.

12 . The apparatus of claim 1 , wherein the non-inclusive caching policy is to indicate that any cache line present in the second cache may but is not guaranteed to also be present in the first cache.

13 . The apparatus of claim 1 , wherein the active processor cores are coupled to one or more of the first cache and the second cache.

14 . The apparatus of claim 1 , wherein a processor, having one or more processor cores, comprises the circuitry and/or the second cache.

15 . The apparatus of claim 1 , wherein a System On Chip (SOC) comprises one or more of: a processor, having one or more processor cores, the circuitry, the first cache, and the second cache.

16 . One or more non-transitory computer-readable media comprising one or more instructions that when executed on at least one processor configure the processor to perform one or more operations to cause:

a first cache, having a higher level than a second cache, to store data; and

circuitry to determine a caching policy between the first cache and the second cache based on a comparison of a number of active processor cores and a threshold value,

wherein the caching policy is one of an inclusive caching policy or a non-inclusive caching policy.

17 . The one or more computer-readable media of claim 16 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the circuitry to dynamically determine the caching policy during runtime.

18 . The one or more computer-readable media of claim 16 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause a machine learning model to determine the threshold value based on telemetry data.

19 . The one or more computer-readable media of claim 18 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause collection of the telemetry data during a selected period of time.

20 . The one or more computer-readable media of claim 18 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the machine learning model to operate in accordance with a logistic regression model.

21 . A method comprising:

causing a first cache, having a higher level than a second cache, to store data; and

determining a caching policy between the first cache and the second cache based on a comparison of a number of active processor cores and a threshold value, wherein the caching policy is one of an inclusive caching policy or a non-inclusive caching policy.

22 . The method of claim 21 , comprising dynamically determining the caching policy during runtime.

23 . The method of claim 21 , further comprising determining, by a machine learning model, the threshold value based on telemetry data.

24 . The method of claim 23 , further comprising collecting the telemetry data during a selected period of time.

25 . The method of claim 23 , further comprising operating the machine learning model in accordance with a logistic regression model.

Assignments (1)

Continuity (1)

References Cited (250)