IP Library › Granted Patent US 12,376,373
Granted Patent B2
US 12,376,373 · App. 17/771,565 · Granted Jul 29, 2025

Semiconductor device

Inventors: Shunpei Yamazaki (Setagaya, JP); Shuhei Nagatsuka (Atsugi, JP); Takuya Kawata (Atsugi, JP); Ryota Hodo (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10D84/83H10B12/00H10B41/70H10D30/6758H10D30/69H10D84/00H10D84/0126H10D84/038
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Quick Facts
Patent No.
US 12,376,373
App. No.
17/771,565
Granted
Jul 29, 2025
Kind
B2
Abstract

A semiconductor device with a small variation in characteristics is provided. The semiconductor device includes a first insulator, a transistor over the first insulator, a second insulator over the transistor, a third insulator over the second insulator, a fourth insulator over the third insulator, and an opening region. The opening region includes the second insulator, the third insulator over the second insulator, and the fourth insulator over the third insulator. The third insulator includes an opening reaching the second insulator. The fourth insulator is in contact with a top surface of the second insulator inside the opening.

Claims (52)

1. A semiconductor device comprising:

a first insulator;

a transistor over the first insulator;

a second insulator over the first insulator;

a third insulator over the second insulator; and

a fourth insulator over the third insulator,

wherein the second insulator comprises a region positioned over the transistor,

wherein the third insulator comprises an opening reaching the second insulator, and

wherein the fourth insulator is in contact with a top surface of the second insulator inside the opening.

2. A semiconductor device comprising:

a first insulator;

a transistor over the first insulator;

a second insulator over the first insulator;

a third insulator over the second insulator; and

a fourth insulator over the third insulator,

wherein the second insulator comprises a region positioned over the transistor,

wherein the third insulator comprises an opening reaching the second insulator,

wherein the fourth insulator is in contact with a top surface of the second insulator inside the opening,

wherein the transistor comprises:

a fifth insulator over the first insulator;

an oxide over the fifth insulator;

a first conductor and a second conductor over the oxide;

a sixth insulator over the first conductor and the second conductor;

a seventh insulator that is over the oxide and placed between the first conductor and the second conductor; and

a third conductor over the seventh insulator, and

wherein the sixth insulator is in contact with the second insulator.

3. The semiconductor device according to claim 1 ,

wherein the fourth insulator is in contact with the first insulator.

4. The semiconductor device according to claim 2 ,

wherein the seventh insulator comprises:

an eighth insulator; and

a ninth insulator over the eighth insulator,

wherein the eighth insulator is in contact with the second insulator, and

wherein the ninth insulator is in contact with the third conductor.

5. The semiconductor device according to claim 1 ,

wherein the first insulator and the fourth insulator each contain silicon and nitrogen.

6. The semiconductor device according to claim 1 ,

wherein the third insulator is AlO x , and

wherein x is a given number greater than 0.

7. The semiconductor device according to claim 4 ,

wherein the fifth insulator and the ninth insulator each contain hafnium.

8. The semiconductor device according to claim 2 ,

wherein the first insulator and the fourth insulator each contain silicon and nitrogen.

9. The semiconductor device according to claim 2 ,

wherein the third insulator and the sixth insulator are each AlO x , and

wherein x is a given number greater than 0.

10. The semiconductor device according to claim 2 ,

wherein the oxide is an oxide semiconductor comprising any one or more selected from In, Ga, and Zn.

11. The semiconductor device according to claim 1 ,

wherein the opening comprises a region not overlapping with the transistor.

12. The semiconductor device according to claim 2 ,

wherein the opening comprises a region not overlapping with the transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2022
From: YAMAZAKI, SHUNPEI; NAGATSUKA, SHUHEI; KAWATA, TAKUYA; HODO, RYOTA
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 059877/0810 →
Priority Claims (2)
JP 2019-200259 · Nov 1, 2019 · national
JP 2020-068169 · Apr 6, 2020 · national
Continuity (1)
Related Publication 20220367450A1 · Nov 17, 2022
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