Granted Patent B2

US 12,745,391 · App. 17/776,388 · Granted Sep 22, 2026

Inventors: Hiromi Sawai (Atsugi, JP); Tsutomu Murakawa (Isehara, JP); Hitoshi Kunitake (Isehara, JP)

Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

H10B43/27H10B41/27H10W20/20

Abstract

Claims (39)

1 . A method for manufacturing a memory device, the memory device comprising:

a first insulator;

a first conductor comprising a first opening over the first insulator;

a second insulator comprising a second opening over the first conductor;

a second conductor comprising a third opening over the second insulator;

a third insulator over the second conductor;

a first semiconductor provided in the first opening to the third opening;

a second semiconductor provided in the first opening to the third opening;

a fourth insulator provided in the first opening to the third opening;

a fifth insulator between the first semiconductor and the second semiconductor provided in the first opening to the third opening; and

a third conductor provided between the first semiconductor and the fourth insulator,

the method comprising:

forming the first insulator;

forming the first conductor over the first insulator;

forming the second insulator over the first conductor;

forming a sixth insulator over the second insulator;

forming the third insulator over the sixth insulator;

forming the third opening in the sixth insulator;

forming the second opening in the second insulator;

forming the first opening in the first conductor;

isotropically etching the first conductor, so that the first conductor has a portion more recessed than a side surface of the first insulator and a side surface of the second insulator;

forming the fourth insulator and the third conductor in the first opening, the second opening, and the third opening, so that the recessed portion of the first conductor is filled with the third conductor with the fourth insulator therebetween:

forming the first semiconductor over the fourth insulator in the first opening, the second opening, and the third opening;

forming the fifth insulator over the first semiconductor in the first opening, the second opening, and the third opening;

forming the second semiconductor over the fifth insulator in the first opening, the second opening, and the third opening;

removing the sixth insulator; and

forming the second conductor between the second insulator and the third insulator,

wherein the first semiconductor comprises a channel formation region of a first transistor,

wherein the second semiconductor comprises a channel formation region of a second transistor, and

wherein the third conductor is in contact with the first semiconductor.

2 . The method for manufacturing a memory device according to claim 1 , wherein the second conductor comprises a material in the first conductor.

3 . The method for manufacturing a memory device according to claim 1 , wherein the second conductor comprises a material different from a material in the first conductor.

4 . The method for manufacturing a memory device according to claim 1 , wherein a diameter of the first opening is larger than a diameter of the second opening and a diameter of the third opening.

5 . The method for manufacturing a memory device according to claim 1 , wherein a diameter of the first opening is made larger than a diameter of the second opening and a diameter of the third opening before the first semiconductor is formed.

6 . The method for manufacturing a memory device according to claim 1 , wherein the first semiconductor comprises an oxide semiconductor.

7 . The method for manufacturing a memory device according to claim 1 , wherein the first semiconductor has crystallinity.

8 . The method for manufacturing a memory device according to claim 7 , wherein the first semiconductor comprises a region where a c-axis is aligned in a direction normal to a side surface of the second conductor in the third opening.

9 . The method for manufacturing a memory device according to claim 1 , further comprising a substrate,

wherein the first insulator is positioned over the substrate.

Assignments (1)

Priority Claims (2)

Continuity (1)

References Cited (43)