IP Library Granted Patent US 12,457,744
Granted Patent B2
US 12,457,744 · App. 17/932,942 · Granted Oct 28, 2025

Three-dimensional memory device and method of making thereof using selective metal nitride deposition on dielectric metal oxide blocking dielectric

Inventors: Tatsuya Hinoue (Yokkaichi, JP); Tomohiro Uno (Yokkaichi, JP)
Assignee: Sandisk Technologies, Inc.
H10B43/27H10B51/20H10B63/34
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,457,744
App. No.
17/932,942
Granted
Oct 28, 2025
Kind
B2
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a set of dielectric-metal-oxide blocking dielectric portions located at levels of the electrically conductive layers, a memory material layer, and a vertical semiconductor channel. Each of the electrically conductive layers includes a tubular metal nitride portion and a metal fill material portion, each of the tubular metal nitride portions laterally surrounds and contacts a respective one of the dielectric-metal-oxide blocking dielectric portions, and each metal fill material portion either contacts respective overlying and underlying insulating layers of the insulating layers, or contacts respective upper and lower metal nitride liner portions which have a smaller thickness than the tubular metal nitride portions.

Claims (14)

1. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers;

a memory opening vertically extending through the alternating stack; and

a memory opening fill structure located in the memory opening and comprising a set of dielectric-metal-oxide blocking dielectric portions located at levels of the electrically conductive layers, a memory material layer, and a vertical semiconductor channel,

wherein:

each of the electrically conductive layers comprises a tubular metal nitride portion and a metal fill material portion;

each of the tubular metal nitride portions of the electrically conductive layers laterally surrounds and contacts a respective one of the dielectric-metal-oxide blocking dielectric portions;

each metal fill material portion either contacts respective overlying and underlying insulating layers of the insulating layers, or contacts respective upper and lower metal nitride liner portions which have a smaller thickness than the tubular metal nitride portions; and

the set of dielectric-metal-oxide blocking dielectric portions comprise discrete dielectric-metal-oxide blocking dielectric portions each of which comprises a respective cylindrical outer sidewall that vertically extends from a respective underlying insulating layer of the insulating layers to a respective overlying insulating layer of the insulating layers, an annular top surface in contact with the respective overlying insulating layer, and an annular bottom surface in contact with the respective underlying insulating layer.

2. The three-dimensional memory device of claim 1 , wherein each of the tubular metal nitride portions comprises a respective cylindrical inner sidewall that contacts an entirety of a cylindrical outer sidewall of a respective one of the discrete dielectric-metal-oxide blocking dielectric portions.

3. The three-dimensional memory device of claim 1 , wherein:

the discrete dielectric-metal-oxide blocking dielectric portions are vertically spaced apart from each other; and

each of the discrete dielectric-metal-oxide blocking dielectric portions is in direct contact with and has a same vertical extent as a respective one of the electrically conductive layers within the alternating stack.

4. The three-dimensional memory device of claim 3 , wherein cylindrical inner sidewalls of the discrete dielectric-metal-oxide blocking dielectric portions are vertically coincident with sidewalls of the insulating layers of the alternating stack that are located around the memory opening.

Assignments (4)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2022
From: HINOUE, TATSUYA; UNO, TOMOHIRO
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 061138/0497 →
Continuity (1)
Related Publication 20240098992A1 · Mar 21, 2024
References Cited (63)
US 9613977B2 · Sharangpani et al. · 2017 [cited by applicant]
US 9659955B1 · Sharangpani et al. · 2017 [cited by applicant]
US 9659956B1 · Pachamuthu et al. · 2017 [cited by applicant]
US 9780182B2 · Peri et al. · 2017 [cited by applicant]
US 9875929B1 · Shukla et al. · 2018 [cited by applicant]
US 9984963B2 · Peri et al. · 2018 [cited by applicant]
US 10283513B1 · Zhou et al. · 2019 [cited by applicant]
US 10438964B2 · Makala et al. · 2019 [cited by applicant]
US 10707233B1 · Cui et al. · 2020 [cited by applicant]
US 10804282B2 · Baraskar et al. · 2020 [cited by applicant]
US 10818542B2 · Cui et al. · 2020 [cited by applicant]
US 10840259B2 · Rabkin et al. · 2020 [cited by applicant]
US 10861869B2 · Nakamura et al. · 2020 [cited by applicant]
US 10916504B2 · Mukae et al. · 2021 [cited by applicant]
US 10991721B2 · Rabkin et al. · 2021 [cited by applicant]
US 11049807B2 · Li et al. · 2021 [cited by applicant]
US 11063063B2 · Zhang et al. · 2021 [cited by applicant]
US 11101288B2 · Zhang et al. · 2021 [cited by applicant]
US 11177280B1 · Rajashekhar et al. · 2021 [cited by applicant]
US 11244953B2 · Kanakamedala et al. · 2022 [cited by applicant]
US 11244958B2 · Cui et al. · 2022 [cited by applicant]
US 11289416B2 · Tsutsumi et al. · 2022 [cited by applicant]
US 20080251851A1 · Pan · 2008 [cited by examiner]
US 20100163968A1 · Kim · 2010 [cited by examiner]
US 20120120728A1 · Kim · 2012 [cited by examiner]
US 20140284695A1 · Won · 2014 [cited by examiner]
US 20160149002A1 · Sharangpani · 2016 [cited by examiner]
US 20160225866A1 · Peri · 2016 [cited by examiner]
US 20160351497A1 · Peri et al. · 2016 [cited by applicant]
US 20160379989A1 · Sharangpani et al. · 2016 [cited by applicant]
US 20170125436A1 · Sharangpani et al. · 2017 [cited by applicant]
US 20180374866A1 · Makala et al. · 2018 [cited by applicant]
US 20200020715A1 · Nakamura et al. · 2020 [cited by applicant]
US 20200051993A1 · Rabkin et al. · 2020 [cited by applicant]
US 20200395310A1 · Mukae et al. · 2020 [cited by applicant]
US 20210159167A1 · Tsutsumi et al. · 2021 [cited by applicant]
US 20210265372A1 · Kanakamedala et al. · 2021 [cited by applicant]
US 20210265385A1 · Rajashekhar et al. · 2021 [cited by applicant]
US 20210335805A1 · Kai et al. · 2021 [cited by applicant]
US 20210335999A1 · Kai et al. · 2021 [cited by applicant]
US 20220052073A1 · Kitazawa et al. · 2022 [cited by applicant]
US 20220059462A1 · Said et al. · 2022 [cited by applicant]
US 20220102379A1 · Liao · 2022 [cited by examiner]
US 20220109003A1 · Nagahata et al. · 2022 [cited by applicant]
Endoh et al., “Novel Ultra High-Density Memory with a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36, doi: 10.1109/IEDM.2001.979396. [cited by applicant]
Zheng, L. et al., “Zheng et. al., Area-Selective Atomic Layer Deposition of TiN Using Trimethoxy(octadecyl)silane as a Passivation Layer,” [cited by applicant]
U.S. Appl. No. 17/155,541, filed Jan. 22, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/192,603, filed Mar. 4, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/192,668, filed Mar. 4, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/317,442, filed May 11, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/345,831, filed Jun. 11, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/345,860, filed Jun. 11, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/348,305, filed Jun. 15, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/348,328, filed Jun. 15, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/351,756, filed Jun. 18, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/351,789, filed Jun. 18, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/351,811, filed Jun. 18, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/378,196, filed Jul. 16, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/406,493, filed Aug. 19, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/587,470, filed Jan. 28, 2022, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/587,518, filed Jan. 28, 2022, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/655,827, filed Mar. 22, 2022, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/663,055, filed May 12, 2022, SanDisk Technologies LLC. [cited by applicant]