IP Library › Granted Patent US 12,541,634
Granted Patent B2
US 12,541,634 · App. 18/110,343 · Granted Feb 3, 2026

Routing non-preferred direction wiring layers of an integrated circuit by minimizing vias between these layers

Inventor: Akira Fujimura (Saratoga, CA)
Assignee: D2S, INC.
G06F30/394G06F30/3947G06F30/3953G06N3/08
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Quick Facts
Patent No.
US 12,541,634
App. No.
18/110,343
Granted
Feb 3, 2026
Kind
B2
Abstract

Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Claims (30)

1 . A method of performing routing for an integrated circuit (IC) design comprising (i) a plurality of non-preferred direction (NPD) routing layers including first and second NPD routing layers and (ii) a plurality of preferred direction (PD) routing layers, the method comprising

defining a first via cost for biasing path searches for the routing against defining a via between the first and second NPD routing layers and a second via cost for biasing the path searches against defining a via between an NPD routing layer and a PD routing layer, wherein the second via cost is more expensive than the first via cost in order to bias the path searches against using the PD routing layers;

using the first and second via costs to perform path searches to identify a plurality of paths to connect a plurality of nets; and

embedding the identified paths as routes that connect the plurality of nets.

2 . The method of claim 1 , wherein by biasing the path searches against defining vias between the first and second NPD routing layers, the first via cost biases the path searches to identify paths for the nets that reside completely or mostly on just one NPD routing layer.

3 . The method of claim 2 further comprising presenting the first via cost as a configurable parameter to a designer in order to allow the designer to modify the first via cost to increase or decrease the biasing towards using just one NPD routing layer for all of an identified path.

4 . The method of claim 1 , wherein the defining, using and embedding are part of a first routing operation that is performed for a first set of nets, the method further comprising performing a second routing operation to identify routes that traverse the PD routing layers to connect nodes associated with a second set of nets that are not part of the first set of nets.

5 . The method of claim 4 further comprising:

identifying a sorted order for a group of nets according to estimated lengths of routes for connecting the nets; and

selecting, based on the sorted order, a subgroup of nets with estimated lengths shorter than a particular value as a plurality of nets to try to route in the first routing operation.

6 . The method of claim 4 , wherein the second set of nets comprises selected nets that the first routing operation is not able to route.

7 . The method of claim 4 , wherein at least a subset of routes identified by the first routing operations are curvilinear routes with at least one curvilinear segment.

8 . The method of claim 4 , wherein at least some of the NPD routes identified by the first routing operation have route segments that traverse in two or more of eight preferred directions of routing.

9 . The method of claim 4 , wherein the first and second routing operations are detailed routing operations.

10 . The method of claim 4 , wherein the first and second routing operations are topological routing operations.

11 . The method of claim 10 further comprising performing a geometric routing operation after the first and second topological routing operations to identify geometric routes for the topological routes produced by the first and second topological routing operations.

12 . The method of claim 1 , wherein the first and second NPD routing layers are third and fourth routing layers of the IC design and the second plurality of routing layers comprises a plurality of routing layers above the fourth routing layer.

13 . The method of claim 12 further comprising defining a third via cost for routes traversing to the third routing layer from a first routing layer or a second routing layer of the IC design; and using the third via cost in performing the path searches.

14 . The method of claim 13 , wherein the first and second routing layers comprise a plurality of regions that have preferred direction rectilinear routing for intellectual property (IP) circuit blocks of the IC design, said path searches using space between said regions to identify NPD routes on the first and second NPD routing layers.

15 . A non-transitory machine readable medium storing a program for performing routing for an integrated circuit (IC) design comprising (i) a plurality of non-preferred direction (NPD) routing layers including first and second NPD routing layers and (ii) a plurality of preferred direction (PD) routing layers, the program comprising sets of instructions for:

defining a first via cost for biasing path searches for the routing against defining a via between the first and second NPD routing layers and a second via cost for biasing the path searches against defining a via between an NPD routing layer and a PD routing layer, wherein the second via cost is more expensive than the first via cost in order to bias the path searches against using the PD routing layers;

using the first and second via costs to perform path searches to identify a plurality of paths to connect a plurality of nets; and

embedding the identified paths as routes that connect the plurality of nets.

16 . The non-transitory machine readable medium of claim 15 , wherein by biasing the path searches against defining vias between the first and second NPD routing layers, the first via cost biases the path searches to identify paths for the nets that reside completely or mostly on just one NPD routing layer.

17 . The non-transitory machine readable medium of claim 16 , wherein the program further comprises a set of instructions for presenting the first via cost as a configurable parameter to a designer in order to allow the designer to modify the first via cost to increase or decrease the biasing towards using just one NPD routing layer for all of an identified path.

18 . The non-transitory machine readable medium of claim 15 , wherein the sets of instructions for defining, using and embedding are part of a first routing operation that is performed for a first set of nets, the program further comprising a set of instructions for performing a second routing operation to identify routes that traverse the PD routing layers to connect nodes associated with a second set of nets that are not part of the first set of nets.

19 . The non-transitory machine readable medium of claim 18 , wherein the program further comprises sets of instructions for:

identifying a sorted order for a group of nets according to estimated lengths of routes for connecting the nets; and

selecting, based on the sorted order, a subgroup of nets with estimated lengths shorter than a particular value as a plurality of nets to try to route in the first routing operation.

20 . The non-transitory machine readable medium of claim 18 , wherein the second set of nets comprises selected nets that the first routing operation is not able to route.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2023
From: FUJIMURA, AKIRA
To: D2S, INC.
Reel/Frame 063974/0516 →
Continuity (4)
Provisional Application 63444553 · Feb 9, 2023
Provisional Application 63337545 · May 2, 2022
Provisional Application 63313269 · Feb 23, 2022
Related Publication 20230281374A1 · Sep 7, 2023
References Cited (161)
US 5187671A · Cobb · 1993 [cited by applicant]
US 5808330A · Rostoker et al. · 1998 [cited by applicant]
US 6407434B1 · Rostoker et al. · 2002 [cited by applicant]
US 6480990B1 · Sharp et al. · 2002 [cited by applicant]
US 6829757B1 · Teig · 2004 [cited by examiner]
US 6928633B1 · Teig et al. · 2005 [cited by applicant]
US 7269817B2 · Heng et al. · 2007 [cited by applicant]
US 7754401B2 · Fujimura et al. · 2010 [cited by applicant]
US 7784010B1 · Balsdon et al. · 2010 [cited by applicant]
US 8473875B2 · Fujimura et al. · 2013 [cited by applicant]
US 8818072B2 · Ong et al. · 2014 [cited by applicant]
US 9257367B2 · Okada et al. · 2016 [cited by applicant]
US 10012900B2 · Kim et al. · 2018 [cited by applicant]
US 10444629B2 · Zable · 2019 [cited by applicant]
US 10520830B2 · Kicken et al. · 2019 [cited by applicant]
US 10670973B2 · Zou et al. · 2020 [cited by applicant]
US 10678142B2 · Jheng et al. · 2020 [cited by applicant]
US 10783292B1 · Clewes et al. · 2020 [cited by applicant]
US 10923318B2 · Gledhill et al. · 2021 [cited by applicant]
US 10949595B2 · Tsutsui et al. · 2021 [cited by applicant]
US 11043359B2 · Nakamura et al. · 2021 [cited by applicant]
US 11132489B1 · Liu et al. · 2021 [cited by applicant]
US 20050132306A1 · Smith et al. · 2005 [cited by applicant]
US 20050138593A1 · Okumura · 2005 [cited by applicant]
US 20050251771A1 · Robles · 2005 [cited by applicant]
US 20060066417A1 · Yamanaga et al. · 2006 [cited by applicant]
US 20060190911A1 · Stivers · 2006 [cited by applicant]
US 20080028352A1 · Birch et al. · 2008 [cited by applicant]
US 20080109766A1 · Song et al. · 2008 [cited by applicant]
US 20080115099A1 · Patra · 2008 [cited by applicant]
US 20110089345A1 · Komagata et al. · 2011 [cited by applicant]
US 20110239181A1 · Uchino · 2011 [cited by applicant]
US 20120151422A1 · White et al. · 2012 [cited by applicant]
US 20130022929A1 · Komagata et al. · 2013 [cited by applicant]
US 20130031524A1 · He et al. · 2013 [cited by applicant]
US 20130159943A1 · Agarwal et al. · 2013 [cited by applicant]
US 20130283216A1 · Pearman et al. · 2013 [cited by applicant]
US 20130283218A1 · Fujimura et al. · 2013 [cited by applicant]
US 20160125120A1 · Yu et al. · 2016 [cited by applicant]
US 20170185711A1 · Fujiwara · 2017 [cited by applicant]
US 20170194126A1 · Bhaskar et al. · 2017 [cited by applicant]
US 20170357911A1 · Liu et al. · 2017 [cited by applicant]
US 20180067900A1 · Mos et al. · 2018 [cited by applicant]
US 20190146355A1 · Jheng et al. · 2019 [cited by applicant]
US 20190197213A1 · Ungar · 2019 [cited by applicant]
US 20190206041A1 · Fang et al. · 2019 [cited by applicant]
US 20190377849A1 · Sha et al. · 2019 [cited by applicant]
US 20190385300A1 · Baidya et al. · 2019 [cited by applicant]
US 20200051781A1 · Fujimura et al. · 2020 [cited by applicant]
US 20200065453A1 · Kim et al. · 2020 [cited by applicant]
US 20200134131A1 · Tien et al. · 2020 [cited by applicant]
US 20200184137A1 · Tsutsui et al. · 2020 [cited by applicant]
US 20200364394A1 · Yu et al. · 2020 [cited by applicant]
US 20200380089A1 · Gheith et al. · 2020 [cited by applicant]
US 20200387660A1 · Cecil · 2020 [cited by applicant]
US 20210048741A1 · Lugg et al. · 2021 [cited by applicant]
US 20210181620A1 · Poonawala et al. · 2021 [cited by applicant]
US 20210216697A1 · Brink et al. · 2021 [cited by applicant]
US 20210279878A1 · Adler et al. · 2021 [cited by applicant]
US 20210397172A1 · Slachter et al. · 2021 [cited by applicant]
US 20220035237A1 · Lee et al. · 2022 [cited by applicant]
US 20220050381A1 · Biswas et al. · 2022 [cited by applicant]
US 20220128899A1 · Fujimura et al. · 2022 [cited by applicant]
US 20220138381A1 · Yamane et al. · 2022 [cited by applicant]
US 20220187713A1 · Middlebrooks et al. · 2022 [cited by applicant]
US 20220299881A1 · Zheng et al. · 2022 [cited by applicant]
US 20230024684A1 · Fujimura et al. · 2023 [cited by applicant]
US 20230027655A1 · Fujimura et al. · 2023 [cited by applicant]
US 20230032510A1 · Fujimura et al. · 2023 [cited by applicant]
US 20230092665A1 · Fujimura et al. · 2023 [cited by applicant]
US 20230107556A1 · Tao et al. · 2023 [cited by applicant]
US 20230153505A1 · Chang et al. · 2023 [cited by applicant]
US 20230168660A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230169245A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230169246A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230169247A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230186009A1 · Fujimura et al. · 2023 [cited by applicant]
US 20230205972A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230214571A1 · Apte et al. · 2023 [cited by applicant]
US 20230229836A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230229840A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230229844A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230267265A1 · Oriordan · 2023 [cited by applicant]
US 20230274065A1 · Fujimura · 2023 [cited by applicant]
US 20230274066A1 · Fujimura · 2023 [cited by applicant]
US 20230274067A1 · Fujimura · 2023 [cited by applicant]
US 20230274068A1 · Fujimura · 2023 [cited by applicant]
US 20230274069A1 · Fujimura · 2023 [cited by applicant]
US 20230274070A1 · Fujimura · 2023 [cited by applicant]
US 20230274071A1 · Fujimura · 2023 [cited by applicant]
US 20230282635A1 · Fujimura · 2023 [cited by applicant]
US 20230297756A1 · Ruic · 2023 [cited by applicant]
US 20230306177A1 · Fujimura · 2023 [cited by applicant]
US 20230351087A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230351088A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230351089A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230359804A1 · Oriordan · 2023 [cited by applicant]
US 20240119214A1 · Oriordan et al. · 2024 [cited by applicant]
CN 107438842A · 2017 [cited by applicant]
CN 111758072A · 2020 [cited by applicant]
CN 113168085A · 2021 [cited by applicant]
CN 113168115A · 2021 [cited by applicant]
EP 3951496A1 · 2022 [cited by applicant]
JP 2005141679A · 2005 [cited by applicant]
JP 2007536581A · 2007 [cited by applicant]
JP 2011204000A · 2011 [cited by applicant]
JP 2014174288A · 2014 [cited by applicant]
JP 2019114295A · 2019 [cited by applicant]
JP 2021509208A · 2021 [cited by applicant]
KR 102170578B1 · 2020 [cited by applicant]
KR 20210010897A · 2021 [cited by applicant]
KR 102377411B1 · 2022 [cited by applicant]
TW I710763B · 2020 [cited by applicant]
TW 202113501A · 2021 [cited by applicant]
TW 202121050A · 2021 [cited by applicant]
WO 2021043936A1 · 2021 [cited by applicant]
WO 2022086825A1 · 2022 [cited by applicant]
WO 2023163910A2 · 2023 [cited by applicant]
Dai, Wayne Wei-Ming, “Rubber band routing and dynamic data representation,” 1990 IEEE International Conference on Computer-Aided Design, Nov. 11-15, 1990, 4 pages, IEEE, Santa Clara, California, USA. [cited by applicant]
Staepelaere, David Joseph, “Geometric Transformations for a Rubber-band Sketch,” Master's Thesis, Sep. 1992, 71 pages, University of California at Santa Cruz, Santa Cruz, CA. [cited by applicant]
Ajayi, Tutu, et al., “OpenROAD: Toward a Self-Driving, Open-Source Digital Layout Implementation Tool Chain,” Proceedings of Government Microcircuit Applications and Critical Technology Conference, Jan. 1, 2019, 6 pages… [cited by applicant]
Ao, Jianchang, et al., “Delay-Driven Layer Assignment in Global Routing under Multi-tier Interconnect Structure,” ISPD '13: Proceedings of the 2013 ACM International Symposium on Physical Design, Mar. 2013, 7 pages, ACM… [cited by applicant]
Author Unknown, “D2S Enables ”Stitchless“ Full-Chip Inverse Lithography Technology in a Single Day for the Multi-Beam Era,” Press Release, Sep. 16, 2019, 3 pages, D2S, Inc., San Jose, California, USA. [cited by applicant]
Author Unknown, “D2S Unveils Industry's First Mask-Wafer Double Simulation Platform,” Press Release, Sep. 20, 2011, 3 pages, D2S, Inc., San Jose, California, USA. [cited by applicant]
Author Unknown, “Deep reinforcement learning,” Wikipedia, Sep. 21, 2020, 2 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “Design rule checking,” Wikipedia, May 27, 2020, 4 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “Marching squares,” Wikipedia, Dec. 30, 2019, 9 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “Multiple patterning,” Wikipedia, Oct. 10, 2020, 22 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “Optical proximity correction,” Wikipedia, Apr. 28, 2019, 5 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “Rasterisation,” Wikipedia, Aug. 21, 2020, 4 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “TrueMask® DS,” Exact Date Unknown but Before May 2020, 3 pages, D2S, Inc., retrieved from https://design2silicon.com/products/truemask-ds/. [cited by applicant]
Author Unknown, “TrueMask® ILT Backgrounder Stitchless Full-Chip ILT in a Day,” Backgrounder, Sep. 2019, 6 pages, D2S, Inc., San Jose, California, USA. [cited by applicant]
Author Unknown, “TrueMask® ILT,” Exact Date Unknown but Before May 2020, 7 pages, D2S, Inc., retrieved from https://design2silicon.com/products/truemask-ilt/. [cited by applicant]
Cecil, Thomas, et al., “Establishing Fast, Practical, Full-Chip ILT Flows Using Machine Learning,” SPIE Proceedings 11327, Optical Microlithography XXXIII, Mar. 23, 2020, 19 pages, vol. 1132706, SPIE, San Jose, Californ… [cited by applicant]
Chen, Kun-Yuan, et al., “Full-Chip Application of Machine Learning SRAFs on DRAM Case Using Auto Pattern Selection,” SPIE Proceedings 10961, Optical Microlithography XXXII, Oct. 10, 2019, 13 pages, vol. 1096108, SPIE, S… [cited by applicant]
Chen, Tai-Chen, “Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction,” Jun. 2007, 13 pages, IEEE, retrieved from http://cc.ee.ntu.edu.tw/˜ywchang/Papers/tcad07-mgr.pdf. [cited by applicant]
Ibtehaz, Nabil, et al., “MultiResUNet: Rethinking the U-Net Architecture for Multimodal Biomedical Image Segmentation,” Feb. 11, 2019, 25 pages, retrieved from https://arxiv.org/pdf/1902.04049.pdf. [cited by applicant]
Jia, Ningning, et al., “Machine Learning for Inverse Lithography: using stochastic gradient descent for robust photomask synthesis,” Journal of Optics, Apr. 1, 2010, 9 pages, vol. 12, IOP Publishing, retrieved from http… [cited by applicant]
Kwan, Joe, et al., “Applying Machine Learning Techniques to Accelerate Advanced Process Yield Ramp,” Jan. 5, 2021, 29 pages, Siemens Digital Industries Software, Munich, Germany. [cited by applicant]
Lin, Yibo, et al., “Machine Learning for Yield Learning and Optimization,” 2018 IEEE International Test Conference (ITC), Oct. 29-Nov. 1, 2018, 10 pages, IEEE, Phoenix, AZ, USA. [cited by applicant]
Liu, Peng, “Mask Synthesis Using Machine Learning Software and Hardware Platforms,” SPIE Proceedings 11327, Optical Microlithography XXXIII, Mar. 23, 2020, 17 pages, vol. 1132707, SPIE, San Jose, California, USA. [cited by applicant]
Mitchell, Robin, “Imec Demonstrates Buried Power Rails in FinFET CMOS,” Mar. 17, 2021, 6 pages, EPM, retrieved from https://www.electropages.com/blog/2021/03/imec-demonstrates-buried-power-rails-finfet-cmos. [cited by applicant]
Mitra, Joydeep, et al., “RADAR: RET-Aware Detailed Routing Using Fast Lithography Simulations,” DAC '05: 42nd annual Design Automation Conference, Jun. 13-17, 2005, 6 pages, IEEE, retrieved from https://citeseerx.ist.ps… [cited by applicant]
Naik, Mehul, “Challenges to Interconnect Scaling at 3nm and Beyond,” Applied Materials, Jun. 14, 2021, 9 pages, Applied Materials, Inc., retrieved from https://www.appliedmaterials.com/us/en/blog/blog-posts/challenges-t… [cited by applicant]
Pang, Linyong (Leo), et al., “Study of Mask and Wafer Co-design That Utilizes a New Extreme SIMD Approach to Computing in Memory Manufacturing: Full-Chip Curvilinear ILT in a Day,” SPIE Proceedings 11148, Photomask Tech… [cited by applicant]
Pang, Linyong, “Inverse Lithography Technology: 30 years from concept to practical, full-chip reality,” Journal of Micro/Nanopatterning, Materials, and Metrology, Aug. 31, 2021, 49 pages, vol. 20(3), SPIE, retrieved fro… [cited by applicant]
Pang, Linyong, et al., “How GPU-Accelerated Simulation Enables Applied Deep Learning for Masks and Wafers,” Photomask Japan 2019: XXVI Symposium on Photomask and Next-Generation Lithography Mask Technology, Apr. 16-18, … [cited by applicant]
Pang, Linyong, et al., “Making Digital Twins using the Deep Learning Kit (DLK),” Photomask Technology 2019, Sep. 15-19, 2019, 13 pages, SPIE, Monterey, California, USA. [cited by applicant]
PCT International Search Report and Written Opinion of Commonly Owned International Patent Application PCT/US2023/013357 (D2S.P0025PCT), mailing date Aug. 15, 2023, 10 pages, International Searching Authority (US). [cited by applicant]
Pradipta, Geraldo, et al., “A Machine Learning Based Parasitic Extraction Tool,” Oct. 31, 2019, 3 pages, University of Minnesota, Minneapolis, Minnesota, USA. [cited by applicant]
Prasad, Divya, “Can we Bury our Scaling Problems with Buried Power Rails and Back-side Power Delivery?,” Mar. 5, 2020, 8 pages, Arm Limited, retrieved from https://community.arm.com/arm-research/b/articles/posts/can-we-… [cited by applicant]
Ren, Haoxing (Mark), “Machine Learning and Deep Learning Applications in Design Automation and Practical Issues,” DAC '19: 56th Annual Design Automation Conference 2019, Jun. 2-6, 2019, 55 pages, Association for Computi… [cited by applicant]
Ronneberger, Olaf, et al., “U-Net: Convolutional Networks for Biomedical Image Segmentation,” May 18, 2015, 8 pages, retrieved from https://arxiv.org/pdf/1505.04597.pdf. [cited by applicant]
Shi, Xuelong, et al., “Physics based feature Vector Design: a Critical Step Towards Machine Learning based Inverse Lithography,” SPIE Proceedings 11327, Optical Microlithography XXXIII, Mar. 23, 2020, 8 pages, vol. 1132… [cited by applicant]
Sole, Marc Pons, “Layout Regularity for Design and Manufacturability,” Doctoral Thesis, Jul. 8, 2012, 185 pages, Technical University of Catalonia, Barcelona, Spain. [cited by applicant]
Sperling, Ed, “Design Rule Complexity Rising,” Semiconductor Engineering—Deep Insights for the Tech Industry, Apr. 19, 2018, 16 pages, SMG, retrieved from https://semiengineering.com/design-rule-complexity-rising/. [cited by applicant]
Teig, Steven L., “The X architecture: not your father's diagonal wiring,” SLIP '02: Proceedings of the 2002 international workshop on System-level interconnect prediction, Apr. 6, 2002, 5 pages, ACM, retrieved from http… [cited by applicant]
Wang, Shibing, et al., “Efficient Full-Chip SRAF Placement Using Machine Learning for Best Accuracy and Improved Consistency,” SPIE Proceedings 10587, Optical Microlithography XXXI, Mar. 20, 2018, 10 pages, vol. 105870N… [cited by applicant]
Wang, Shibing, et al., “Machine Learning Assisted SRAF Placement for Full Chip,” SPIE Proceedings 10451, Photomask Technology 2017, Oct. 16, 2017, 8 pages, vol. 104510D, SPIE, Monterey, California, USA. [cited by applicant]
Yang, Dingcheng, et al., “CNN-Cap: Effective Convolutional Neural Network Based Capacitance Models for Full-Chip Parasitic Extraction,” Jul. 14, 2021, 9 pages, retrieved from https://arxiv.org/pdf/2107.06511.pdf. [cited by applicant]
Shao, Hao-Chiang, et al., “From IC Layout to Die Photograph: A CNN-Based Data-Driven Approach” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, No. 5, May 2021, pp. 957-970, IEEE. [cited by applicant]