Semiconductor chip and semiconductor package including the same
Provided are a semiconductor chip with a reduced thickness and improved reliability, and a semiconductor package including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, an integrated device layer on the semiconductor substrate, a multi-wiring layer on the integrated device layer, and a pad metal layer of a plurality of pad metal layers on the multi-wiring layer, and having test pads defined therein. The pad metal layers extend in a first direction parallel to a top surface of the semiconductor substrate or in a second direction perpendicular to the first direction. A test pad is a central portion of the pad metal layer and, and an outer portion of the pad metal layer excluding the test pad overlaps the wires in a third direction perpendicular to the top surface of the semiconductor substrate.
1 . A semiconductor chip comprising:
a semiconductor substrate;
an integrated device layer on the semiconductor substrate, wherein integrated devices are in the integrated device layer;
a multi-wiring layer on the integrated device layer and having at least two layers of wires; and
a pad metal layer on the multi-wiring layer, electrically connected to the wires of the multi-wiring layer, and has test pads therein,
wherein the pad metal layer extends in a first direction parallel to a top surface of the semiconductor substrate or in a second direction perpendicular to the first direction,
wherein a test pad of the test pads comprises a central portion of the pad metal layer and is exposed by a protective layer that overlaps the pad metal layer,
wherein an outer portion of the pad metal layer excluding the test pad overlaps the wires in a third direction perpendicular to the top surface of the semiconductor substrate;
wherein the multi-wiring layer comprises an isolation region that overlaps the test pad in the third direction,
wherein the wires are not in the isolation region of the multi-wiring layer;
wherein bump pads are on a central portion of a top surface of the semiconductor chip, and
wherein the test pads are on an outer portion of the top surface of the semiconductor chip.
2 . The semiconductor chip of claim 1 , wherein the pad metal layer is electrically connected to an uppermost wire of the multi-wiring layer through at least two via contacts, and
wherein the at least two via contacts are on the outer portion of the pad metal layer.
3 . The semiconductor chip of claim 1 , wherein the pad metal layer has a first shape having a substantially uniform thickness in the first direction and the second direction, or the pad metal layer has a second shape in which the central portion of the pad metal layer corresponding to the test pad is recessed.
4 . The semiconductor chip of claim 3 , wherein the pad metal layer has the first shape, and
wherein the pad metal layer has a thickness of 1.5 μm or less.
5 . The semiconductor chip of claim 3 , wherein the pad metal layer has the second shape,
wherein the test pad has a thickness of 1.5 μm or less, and
wherein the outer portion of the pad metal layer has a thickness of 2 μm or greater.
6 . The semiconductor chip of claim 1 , wherein the semiconductor chip comprises a dynamic random-access memory (DRAM) chip, and
wherein the integrated device layer comprises DRAM devices and through electrodes.
7 . A semiconductor package comprising:
a first semiconductor chip; and
at least one second semiconductor chip stacked on the first semiconductor chip,
wherein the at least one second semiconductor chip comprises a semiconductor chip of claim 1 .
8 . The semiconductor package of claim 7 , wherein the at least one second semiconductor chip is a high bandwidth memory (HBM) package,
wherein the first semiconductor chip comprises a buffer chip, and
wherein the at least one second semiconductor chip comprises a DRAM chip and comprises a plurality of second semiconductor chips.