Granted Patent B2

US 12,690,438 · App. 18/217,898 · Granted Jul 21, 2026

Inventors: Ankur Aggarwal (Pleasanton, CA); Jeremy Matthew Plunkett (San Jose, CA)

Assignee: Celestial AI Inc.

H10W20/20H10W70/635H10W70/05H10W70/60H10W70/65H10W70/652H10W72/242H10W72/244H10W72/252H10W72/922H10W72/9223H10W72/923H10W72/934H10W72/942H10W72/952

Abstract

Claims (34)

1 . A method comprising:

forming a partial through-substrate via (TSV) plug in a front side of a wafer, the wafer comprising an insulating layer and a substrate, the partial TSV plug having a front side, a back side, and a body that increases from the front side to the back side;

etching a cavity in a back side of the wafer that exposes the back side of the partial TSV plug and a portion of a front side interconnect positioned at least partially in the insulating layer of the wafer; and

depositing a conductive material to create a first electrical contact that connects the exposed portion of the front side interconnect to the back side of the wafer and to create a second electrical contact on the exposed back side of the partial TSV plug while maintaining electrical isolation between the second electrical contact on the partial TSV plug and the first electrical contact on the exposed portion of the front side interconnect.

2 . The method of claim 1 , wherein exposing the back side of the partial TSV plug and a portion of the front side interconnect in the common etched cavity further comprises applying a directional anisotropic etch to the etched back side of the wafer.

3 . The method of claim 1 , further comprising adding a protective insulation layer to the conductive material, the protective insulation layer having a connection region formed therein.

4 . The method of claim 1 , wherein the partial TSV plug has a back side horizontal dimension and a front side horizontal dimension, and wherein the back side horizontal dimension is greater than the front side horizontal dimension.

5 . The method of claim 4 , wherein the back side horizontal dimension of the plug at a widest location is at least 10% greater than the front side horizontal dimension.

6 . The method of claim 5 , wherein the back side horizontal dimension of the plug at the widest location is at least 40% greater than the front side horizontal dimension.

7 . The method of claim 1 , wherein forming the partial TSV plug in the front side of the wafer further comprises applying a plasma to the back side of the wafer to create a void.

8 . The method of claim 1 , wherein the back side of the partial TSV plug extends into one or more of the insulating layer, a front side interconnect, or an SOI layer.

9 . The method of claim 1 , wherein the back side of the partial TSV plug extends through the front side of the wafer and partially into the substrate.

10 . The method of claim 1 , further comprising depositing a seed or barrier metal to the etched back side of the wafer including the exposed back side of the partial TSV plug and the exposed portion of the front side interconnect.

11 . The method of claim 10 , wherein an additional conductive material adjacent to the seed or barrier metal on the back side of the partial TSV plug or the exposed portion of the front side interconnect forms a gap on one or more sides of the partial TSV plug such that the front side interconnect and the partial TSV plug are electrically isolated.

12 . The method of claim 11 , wherein depositing the conductive material creates a gap between the exposed portion of the front side interconnect and the exposed back side of the partial TSV plug.

13 . The method of claim 12 , further comprising adding a first conductive connection to the front side interconnect.

14 . The method of claim 13 , further comprising adding a second conductive connection to the partial TSV plug.

15 . The method of claim 14 , wherein one or more of the first conductive connection and the second conductive connection is selected from the group consisting of a solder ball and a copper pillar.

16 . A wafer comprising:

an insulating layer;

a substrate below the insulating layer;

a front side interconnect extending toward a back side of the insulating layer;

a partial TSV plug extending from a front side of the wafer in or above the insulating layer into a portion of the substrate, the partial TSV plug having a back side horizontal dimension and a front side horizontal dimension, and wherein the back side horizontal dimension increases from the front side to the back side;

a first conductive material connected to a back side of the partial TSV plug to connect the partial TSV plug to a first surface on a back side of the wafer; and

a second conductive material connected to a portion of the front side interconnect to connect the front side interconnect to a second surface on the back side of the wafer, the first conductive material being electrically isolated from the second conductive material.

17 . The wafer of claim 16 , wherein the back side horizontal dimension is at least at least 10% greater than the front side horizontal dimension.

18 . The wafer of claim 17 , further comprising a back side insulation layer below the conductive layer with a connection through to the conductive layer.

19 . The wafer of claim 18 , further comprising a seed or barrier metal connected to the back side of the partial TSV plug and the portion of the front side interconnect.

20 . The wafer of claim 19 , wherein an additional conductive material adjacent to the seed or barrier metal on the back side of the partial TSV plug or the portion of the front side interconnect forms a gap on one or more sides of the partial TSV plug such that the front side interconnect and the partial TSV plug are electrically isolated.

21 . A method for forming a via in a wafer, comprising:

performing a front-side process on a front-side of the wafer, including forming a partial through-substrate via (TSV) plug with a variable dimension so that a largest dimension of the partial TSV plug is opposite the front-side of the wafer, wherein the partial TSV plug has a back side horizontal dimension and a front side horizontal dimension, and wherein the back side horizontal dimension is greater than the front side horizontal dimension, and wherein the back side horizontal dimension of the partial TSV plug is at least 10% greater than the front side horizontal dimension of the partial TSV plug; and

performing a back-side process on a back-side of the wafer including:

etching a cavity that exposes the largest dimension of the partial TSV plug and a portion of a front side interconnect in a common etched cavity; and

depositing a conductive material to connect the exposed portion of the front side interconnect to the back-side of the wafer and to connect the exposed largest dimension of the partial TSV plug to the back-side of the wafer.

Assignments (2)

Continuity (6)

References Cited (400)