3D semiconductor devices and structures with transistors
A semiconductor device including: a plurality of transistors, where at least one of the transistors includes a first single crystal source, channel, and drain, where at least one of the transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the transistors includes a fourth single crystal source, channel, and drain, where the fourth single crystal source, channel, and drain is disposed above the third single crystal source, channel, and drain, and where the fourth drain is aligned to the first drain with less than 40 nm misalignment.
1. A semiconductor device, the device comprising:
a plurality of transistors,
wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain,
wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain,
wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain,
wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain,
wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain,
wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and
wherein said fourth single crystal source, channel, and drain is disposed above said third single crystal source, channel, and drain, and
wherein said fourth drain is aligned to said first drain with less than 40 nm misalignment.
2. The device according to claim 1 ,
wherein said first single crystal channel is self-aligned to said second single crystal channel being processed following the same lithography step.
3. The device according to claim 1 , further comprising:
at least one region of oxide to oxide bonds.
4. The device according to claim 1 , further comprising:
an ohmic connection between said first single crystal source or drain and said second single crystal source or drain.
5. The device according to claim 1 ,
wherein at least one of said plurality of transistors comprises a gate all around structure.
6. The device according to claim 1 ,
wherein at least one of said plurality of transistors comprises two side gates.
7. The device according to claim 1 , further comprising:
a two-sided gate structure, and
wherein said two-sided gate structure controls at least one of said first single crystal channels and at least one of said second single crystal channels.
8. A semiconductor device, the device comprising:
a plurality of transistors,
wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain,
wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain,
wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain,
wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain,
wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain,
wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and
wherein at least one of said plurality of transistors comprises a gate all around structure.
9. The device according to claim 8 ,
wherein said first single crystal source or drain, and said second single crystal source or drain, each comprise n+doped regions.
10. The device according to claim 8 , further comprising:
at least one region of oxide to oxide bonds.
11. The device according to claim 8 ,
wherein said first single crystal source is electrically connected to said second single crystal source.
12. The device according to claim 8 ,
wherein said third single crystal channel is self-aligned to said fourth single crystal channel being processed following the same lithography step.
13. The device according to claim 8 , further comprising:
a first gate structure,
wherein said first gate structure controls at least one of said first single crystal channels and at least one of said second single crystal channels.
14. The device according to claim 8 , further comprising:
a first gate structure,
wherein said first gate structure controls at least one of said first single crystal channels and at least one of said third single crystal channels.
15. A semiconductor device, the device comprising:
a plurality of transistors,
wherein at least one of said plurality of transistors comprises a first single crystal channel,
wherein at least one of said plurality of transistors comprises a second single crystal channel,
wherein said second single crystal channel is disposed above said first single crystal channel,
wherein at least one of said plurality of transistors comprises a third single crystal channel,
wherein said third single crystal channel is disposed above said second single crystal channel,
wherein at least one of said plurality of transistors comprises a fourth single crystal channel,
wherein said fourth single crystal channel is disposed above said third single crystal channel,
wherein said least one of said plurality of transistors is a horizontally oriented transistor; and
wherein said device comprise at least one region of oxide to oxide bonds.
16. The device according to claim 15 ,
wherein said first single crystal channel is self-aligned to said second single crystal channel being processed following the same lithography step.
17. The device according to claim 15 ,
wherein formation of said fourth single crystal channel comprises a layer transfer process, and
wherein said layer transfer process will show a bonding interface surface in a decorated cross-sectional SEM.
18. The device according to claim 15 ,
wherein at least one of said plurality of transistors comprises a gate all around structure.
19. The device according to claim 15 , further comprising:
a first gate structure,
wherein said first gate structure controls at least one of said first single crystal channels and at least one of said second single crystal channels.
20. The device according to claim 15 , further comprising:
a first gate structure,
wherein said first gate structure controls at least one of said first single crystal channels and at least one of said third single crystal channels.