IP Library Granted Patent US 12,347,798
Granted Patent B2
US 12,347,798 · App. 18/238,082 · Granted Jul 1, 2025

Semiconductor device, manufacturing method, solid state image sensor, and electronic equipment

Inventor: Masaki Haneda (Kanagawa, JP)
Assignee: Sony Group Corporation
H01L24/05H01L21/3205H01L21/768H01L23/522H01L23/532H01L24/08H01L24/80H01L24/89H01L25/0657H10F39/018H10F39/809H10F39/811H10F99/00H01L24/03H01L2224/0345H01L2224/0346H01L2224/03616H01L2224/05007H01L2224/05082H01L2224/05147H01L2224/05181H01L2224/05186H01L2224/05618H01L2224/05639H01L2224/05655H01L2224/05657H01L2224/0566H01L2224/0801H01L2224/08121H01L2224/08145H01L2224/08147H01L2224/80009H01L2224/80097H01L2224/80895H01L2224/80896H01L2224/80948H01L2224/80986H01L2924/01012H01L2924/01013H01L2924/01023H01L2924/01025H01L2924/0104H01L2924/05442
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Quick Facts
Patent No.
US 12,347,798
App. No.
18/238,082
Granted
Jul 1, 2025
Kind
B2
Abstract

Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.

Claims (54)

1. A semiconductor device comprising:

a first section including a first semiconductor substrate and a first wiring layer;

a second section including a second semiconductor substrate and a second wiring layer, wherein the first section and the second section are stacked; and

a film disposed at an interface between the first section and the second section,

wherein the first wiring layer includes a first connection pad and a first insulating film,

wherein the second wiring layer includes a second connection pad and a second insulating film,

wherein a first portion of the first connection pad contacts a first portion of the second connection pad,

wherein a second portion of the first connection pad contacts a first portion of the film,

wherein a second portion of the second connection pad contacts a second portion of the film,

wherein the film includes a third portion that contacts the first insulating film and the second insulating film, and

wherein the first connection pad is offset from the second connection pad in a direction that is parallel to the interface between the first section and the second section.

2. The semiconductor device of claim 1 , wherein the first connection pad and the second connection pad are bonded to one another, and wherein, in a plan view, a fourth portion of the film overlaps with part of the first connection pad but not part of the second connection pad.

3. The semiconductor device of claim 1 , wherein the first connection pad and the second connection pad include a same metal.

4. The semiconductor device of claim 1 , wherein the first connection pad and the second connection pad each include Cu.

5. The semiconductor device of claim 1 , wherein the film is disposed on at least a side surface of the first connection pad or the second connection pad.

6. The semiconductor device of claim 1 , further comprising a first barrier metal, wherein at least a part of the first barrier metal is between the first connection pad and the first insulating film.

7. The semiconductor device of claim 6 , further comprising a second barrier metal, wherein at least a part of the second barrier metal is between the second connection pad and the second insulating film.

8. The semiconductor device of claim 7 , wherein a first portion of the first barrier metal contacts a third portion of the second connection pad, and wherein a second portion of the first barrier metal contacts a third portion of the film.

9. The semiconductor device of claim 8 , wherein a first portion of the second barrier metal contacts a third portion of the first connection pad, and wherein a second portion of the second barrier metal contacts a fourth portion of the film.

10. The semiconductor device of claim 8 , wherein the first portion of the first barrier metal and the second portion of the first barrier metal are on opposite sides of the first connection pad.

11. The semiconductor device of claim 1 , further comprising:

a pixel region that includes a photodiode, wherein the first connection pad and the second connection pad are disposed in a peripheral region other than the pixel region.

12. The semiconductor device of claim 1 , wherein the first and second connection pads are rectangular in a cross sectional view.

13. The semiconductor device of claim 1 , wherein the film has a thickness ranging from 0.1 nm to 10 nm.

14. A light detecting device comprising:

a first section including a first semiconductor substrate and a first wiring layer;

a second section including a second semiconductor substrate and a second wiring layer, wherein the first section and the second section are stacked;

a film disposed at an interface between the first section and the second section; and

a pixel region that includes a photodiode,

wherein the first wiring layer includes a first connection pad and a first insulating film,

wherein the second wiring layer includes a second connection pad and a second insulating film,

wherein a first portion of the first connection pad contacts a first portion of the second connection pad,

wherein a second portion of the first connection pad contacts a first portion of the film,

wherein a second portion of the second connection pad contacts a second portion of the film, and

wherein the first connection pad and the second connection pad are disposed in a peripheral region other than the pixel region.

15. The light detecting device of claim 14 , wherein the first connection pad and the second connection pad are bonded to one another.

16. The light detecting device of claim 14 , wherein the film is disposed on at least a side surface of the first connection pad or the second connection pad.

17. The light detecting device of claim 14 , further comprising:

a first barrier metal, wherein at least a part of the first barrier metal is between the first connection pad and the first insulating film; and

a second barrier metal, wherein at least a part of the second barrier metal is between the second connection pad and the second insulating film,

wherein a first portion of the first barrier metal contacts a third portion of the second connection pad, and wherein a second portion of the first barrier metal contacts a third portion of the film.

18. The light detecting device of claim 17 , wherein the first barrier metal or the second barrier metal includes tantalum.

19. The light detecting device of claim 17 , wherein the first portion of the first barrier metal and the second portion of the first barrier metal are on opposite sides of the first connection pad.

20. An apparatus comprising:

a first section including a first semiconductor substrate and a first wiring layer;

a second section including a second semiconductor substrate and a second wiring layer, wherein the first section and the second section are stacked;

a film disposed at an interface between the first section and the second section; and

a pixel region that includes a photodiode,

wherein the first wiring layer includes a first connection pad and a first insulating film,

wherein the second wiring layer includes a second connection pad and a second insulating film,

wherein a first portion of the first connection pad contacts a first portion of the second connection pad,

wherein a second portion of the first connection pad contacts a first portion of the film,

wherein a second portion of the second connection pad contacts a second portion of the film, and

wherein the first connection pad and the second connection pad are disposed in a peripheral region other than the pixel region.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2023
From: HANEDA, MASAKI
To: SONY GROUP CORPORATION
Reel/Frame 064705/0502 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2023
From: HANEDA, MASAKI
To: SONY CORPORATION
Reel/Frame 064705/0797 →
CHANGE OF NAME Recorded Aug 25, 2023
From: SONY CORPORATION
To: SONY GROUP CORPORATION
Reel/Frame 064729/0016 →
Priority Claims (1)
JP 2015-104705 · May 22, 2015 · national
Continuity (5)
Continuation 17180359 · Feb 19, 2021
Continuation 16830916 · Mar 26, 2020
Continuation 16297167 · Mar 8, 2019
Continuation 15574207
Related Publication 20230402411A1 · Dec 14, 2023
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