IP Library › Granted Patent US 12,751,079
Granted Patent B2
US 12,751,079 · App. 18/350,933 · Granted Sep 29, 2026

Method for forming a semiconductor device by recessing semiconductor layers and inner spacers

Inventor: Ta-Chun Lin (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10D84/83H10D30/014H10D30/0195H10D30/43H10D30/503H10D30/506H10D30/6735H10D62/121H10D64/015H10D64/017H10D64/018H10D64/258H10D64/518H10D84/0167H10D84/0184H10D84/8311H10D84/8316H10D84/851H10D30/6757
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Quick Facts
Patent No.
US 12,751,079
App. No.
18/350,933
Granted
Sep 29, 2026
Kind
B2
Abstract

A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate. The fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner. The method also includes partially removing the fin structure to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers and forming multiple inner spacers covering the side surfaces of the sacrificial layers. The method further includes recessing the semiconductor layers from the side surfaces of the semiconductor layers after the inner spacers are formed and partially removing the inner spacers so that each of the inner spacers becomes thinner. In addition, the method includes forming an epitaxial structure on the side surfaces of the semiconductor layers.

Claims (62)

1 . A method for forming a semiconductor device structure, comprising:

forming a fin structure over a substrate, wherein the fin structure has a plurality of sacrificial layers and a plurality of semiconductor layers laid out in an alternating manner;

partially removing the fin structure to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers;

forming a dummy gate stack wrapped around the fin structure;

forming gate spacers over sidewalls of the dummy gate stack before the recess is formed;

forming a plurality of inner spacers covering the side surfaces of the sacrificial layers;

recessing the semiconductor layers from the side surfaces of the semiconductor layers after the inner spacers are formed;

partially removing the inner spacers so that each of the inner spacers becomes thinner;

forming an epitaxial structure on the side surfaces of the semiconductor layers;

forming a second fin structure over the substrate, wherein the second fin structure has a plurality of second sacrificial layers and a plurality of second semiconductor layers laid out in an alternating manner, and the dummy gate stack is wrapped around the second fin structure;

partially removing the second fin structure to form a second recess exposing side surfaces of the second semiconductor layers and the second sacrificial layers;

forming a plurality of second inner spacers covering the side surfaces of the second sacrificial layers;

forming a second epitaxial structure on the side surfaces of the second semiconductor layers, wherein the epitaxial structure and the second epitaxial structure have opposite conductivity types; and

partially removing the gate spacers so that portions of the gate spacers near the fin structure become thinner before the epitaxial structure is formed, wherein the gate spacers are partially removed using an etching process, and second portions of the gate spacers near the second fin structure are prevented from being etched by the etching process.

2 . The method for forming a semiconductor device structure as claimed in claim 1 , further comprising:

partially removing the gate spacers so that portions of the gate spacers become thinner before the epitaxial structure is formed.

3 . The method for forming a semiconductor device structure as claimed in claim 1 , wherein the inner spacers are partially removed using an etching process, and the second inner spacers are prevented from being etched by the etching process.

4 . The method for forming a semiconductor device structure as claimed in claim 1 , wherein the recessing of the semiconductor layers from the side surfaces of the semiconductor layer is performed using an etching process, and the second semiconductor layers are prevented from being etched by the etching process.

5 . The method for forming a semiconductor device structure as claimed in claim 1 ,

wherein the gate spacers are partially removed before the inner spacers are partially removed.

6 . The method for forming a semiconductor device structure as claimed in claim 1 ,

wherein the gate spacers and the inner spacers are partially removed simultaneously.

7 . The method for forming a semiconductor device structure as claimed in claim 1 , further comprising:

recessing the sacrificial layers from the side surfaces of the sacrificial layers before the inner spacers are formed.

8 . A method for forming a semiconductor device structure, comprising:

forming a first fin structure and a second fin structure over a substrate, wherein each of the first fin structure and the second fin structure has a plurality of sacrificial layers and a plurality of semiconductor layers laid out in an alternating manner;

partially removing the first fin structure and the second fin structure to form a plurality of recesses exposing side surfaces of the semiconductor layers and the sacrificial layers;

forming a plurality of inner spacers covering the side surfaces of the sacrificial layers of the first fin structure and the second fin structure;

forming n-type doped epitaxial structures on the side surfaces of the semiconductor layers of the first fin structure;

recessing the semiconductor layers of the second fin structure after the n-type doped epitaxial structures are formed;

trimming the inner spacers covering the side surfaces of the sacrificial layers of the second fin structure; and

forming p-type doped epitaxial structures on the side surfaces of the semiconductor layers of the second fin structure.

9 . The method for forming a semiconductor device structure as claimed in claim 8 , wherein the inner spacers covering the side surfaces of the sacrificial layers of the second fin structure are trimmed after the n-type doped epitaxial structures are formed.

10 . The method for forming a semiconductor device structure as claimed in claim 8 , further comprising:

forming a dummy gate stack extending across the first fin structure and the second fin structure; and

forming gate spacers over sidewalls of the dummy gate stack before the recesses are formed.

11 . The method for forming a semiconductor device structure as claimed in claim 10 , further comprising:

forming a mask element covering the first fin structure, the n-type doped epitaxial structures, and a first portion of the gate spacers near the first fin structure; and

trimming the gate spacers so that a second portion of the gate spacers becomes thinner after the mask element is formed.

12 . The method for forming a semiconductor device structure as claimed in claim 10 , further comprising:

removing the dummy gate stack and the sacrificial layers to release a plurality of first semiconductor nanostructures constructed by remaining portions of the semiconductor layers of the first fin structure and a plurality of second semiconductor nanostructures constructed by remaining portions of the semiconductor layers of the second fin structure; and

forming a metal gate stack wrapped around the first semiconductor nanostructures and the second semiconductor nanostructures.

13 . The method for forming a semiconductor device structure as claimed in claim 12 , wherein each of the second semiconductor nanostructures is thicker than each of the first second semiconductor nanostructures.

14 . A method for forming a semiconductor device structure, comprising:

forming a plurality of sacrificial layers and a plurality of semiconductor layers laid out in an alternating manner;

forming a plurality of inner spacers covering side surfaces of the sacrificial layers;

forming a plurality of second sacrificial layers and a plurality of second semiconductor layers laid out in an alternating manner;

forming a first epitaxial structure on side surfaces of the second semiconductor layer;

recessing the semiconductor layers from side surfaces of the semiconductor layers after the inner spacers and the first epitaxial structure are formed;

trimming the inner spacers after the recessing of the semiconductor layers; and

forming a second epitaxial structure on the side surfaces of the semiconductor layers, wherein the second epitaxial structure and the first epitaxial structure have opposite conductivity type.

15 . The method for forming a semiconductor device structure as claimed in claim 14 , further comprising:

forming a dummy gate stack wrapped around the sacrificial layers and the semiconductor layers;

forming gate spacers over sidewalls of the dummy gate stack before the inner spacers are formed; and

partially removing the gate spacers so that portions of the gate spacers become thinner before the second epitaxial structure is formed.

16 . The method for forming a semiconductor device structure as claimed in claim 15 , wherein the gate spacers are partially removed before the inner spacers are trimmed.

17 . The method for forming a semiconductor device structure as claimed in claim 15 , wherein the partial removal of the gate spacers and the trimming of the inner spacers are performed simultaneously.

18 . The method for forming a semiconductor device structure as claimed in claim 15 , wherein the gate spacers are partially removed while a mask element covers the first epitaxial structure, the second sacrificial layers and the second semiconductor layers.

19 . The method for forming a semiconductor device structure as claimed in claim 14 , further comprising:

forming a mask element covering the first epitaxial structure, the second sacrificial layers and the second semiconductor layers before the recessing of the semiconductor layers from the side surfaces of the semiconductor layers.

20 . The method for forming a semiconductor device structure as claimed in claim 19 , further comprising:

removing the mask element after the trimming of the inner spacers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2023
From: LIN, TA-CHUN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 064225/0474 →
Continuity (1)
Related Publication 20250022877A1 · Jan 16, 2025
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