Three-dimensional memory device containing integrated contact-and-support assemblies and methods of making the same
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures including a vertical channel and memory elements located in the memory openings, a contact via cavity vertically extending through the alternating stack, and an integrated contact-and-support assembly located in the contact via cavity. The integrated contact-and-support assembly includes a dielectric support pillar and a conductive layer contact via structure electrically contacting a top surface of a first electrically conductive layer of the electrically conductive layers that surrounds the contact via cavity. A dielectric spacer is located in the contact via cavity, covering a sidewall of the first electrically conductive layer in the contact via cavity, and extending above the top surface of the first electrically conductive layer.
1 . A semiconductor structure, comprising:
an alternating stack of insulating layers and electrically conductive layers;
memory openings vertically extending through the alternating stack;
memory opening fill structures located in the memory openings, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements located at levels of the electrically conductive layers;
a contact via cavity vertically extending through the alternating stack; and
an integrated contact-and-support assembly located in the contact via cavity,
wherein:
the integrated contact-and-support assembly comprises a dielectric support pillar and a conductive layer contact via structure electrically contacting a top surface of a first electrically conductive layer of the electrically conductive layers that surrounds the contact via cavity; and
a dielectric spacer located in the contact via cavity, covering a sidewall of the first electrically conductive layer in the contact via cavity, and extending above the top surface of the first electrically conductive layer.
2 . The semiconductor structure of claim 1 , wherein the dielectric support pillar comprises:
a vertically-extending dielectric material portion that extends through a first subset of the electrically conductive layers that underlie the first electrically conductive layer; and
a plurality of annular dielectric fin portions laterally protruding outward from the vertically-extending dielectric material portion and located at levels of a subset of the insulating layers that underlie the first electrically conductive layer.
3 . The semiconductor structure of claim 2 , wherein:
the vertically-extending dielectric material portion comprises a tubular material portion having an inner cylindrical sidewall that vertically extends continuously through a plurality of electrically conductive layers;
the integrated contact-and-support assembly further comprises a dielectric liner having an outer cylindrical sidewall that contacts the inner cylindrical sidewall of the vertically-extending dielectric material portion of the dielectric support pillar; and
the dielectric spacer comprises an upper portion of the dielectric liner.
4 . The semiconductor structure of claim 3 , wherein the conductive layer contact via structure further comprises a lower portion that is laterally surrounded by the dielectric liner and vertically extends continuously through the first subset of the electrically conductive layers.
5 . The semiconductor structure of claim 3 , wherein:
the vertically-extending dielectric material portion and the dielectric liner vertically extend through the contact via opening in the first electrically conductive layer;
the first electrically conductive layer has a uniform vertical thickness;
a conductive annular pad is located on and protrudes above an annular portion of the top surface of the first electrically conductive layer that laterally surrounds the contact via opening; and
the conductive layer contact via structure directly physically contacts the conductive annular pad.
6 . The semiconductor structure of claim 5 , wherein the conductive annular pad comprises a contoured top surface including an annular planar surface segment and a convex tapered annular surface segment that is adjoined to an inner periphery of the annular planar surface segment and having a convex vertical cross-sectional profile and an annular top-down profile.
7 . The semiconductor structure of claim 3 , wherein:
the dielectric liner completely fills the contact via cavity at a level of the conductive annular pad, and embeds an air gap below the first electrically conductive layer; and
a bottommost surface segment of the conductive layer contact via structure contacts a top surface of the dielectric liner.
8 . The semiconductor structure of claim 2 , wherein the dielectric spacer comprises an upper portion of the dielectric support pillar.
9 . The semiconductor structure of claim 8 , wherein the upper portion of the dielectric support pillar comprises a contoured top surface which comprises an annular topmost surface segment, a cylindrical surface segment having a top periphery that is adjoined to an outer periphery of the annular top surface segment, and a recessed annular surface segment that is adjoined to a bottom periphery of the cylindrical surface segment.
10 . The semiconductor structure of claim 8 , wherein the dielectric spacer protrudes into a recess in a bottom portion of the conductive layer contact via structure.
11 . The semiconductor structure of claim 8 , further comprising:
insulating spacers located on vertically-extending surface segments of stepped surfaces of the alternating stack; and
a dielectric etch stop layer located over horizontally-extending surface segments of the stepped surfaces and over the insulating spacers.
12 . The semiconductor structure of claim 1 , wherein:
the alternating stack comprises a staircase region in which lateral extents of the electrically conductive layers decrease with a vertical distance from a substrate underlying the alternating stack;
a retro-stepped dielectric material potion overlies stepped surfaces of the alternating stack that are located in the staircase region; and
the conductive layer contact via structure vertically extends through the retro-stepped dielectric material portion.
13 . A method of forming a semiconductor structure, comprising:
forming an alternating stack of insulating layers and sacrificial material layers;
forming memory stack structures through the alternating stack, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements formed at levels of the sacrificial material layers;
forming a stepped via cavity through the alternating stack such that an annular surface of a first sacrificial material layer of the sacrificial material layers around the stepped via cavity is physically exposed;
forming a sacrificial annular plate by selectively growing a sacrificial plate material from the physically exposed annular surface of the first sacrificial material layer;
replacing the sacrificial material layers with electrically conductive layers and replacing the sacrificial annular plate with a conductive annular pad located on a first electrically conductive layer; and
forming a conductive layer contact via structure that contacts the conductive annular pad.
14 . The method of claim 13 , further comprising:
forming an in-process integrated contact-and-support assembly in the stepped via cavity, wherein the in-process integrated contact-and-support assembly comprises a dielectric support pillar and a sacrificial via fill material portion; and
replacing the sacrificial via fill material portion with the conductive layer contact via structure to form an integrated contact-and-support assembly comprising the dielectric support pillar and the conductive layer contact via structure.
15 . The method of claim 14 , further comprising:
forming stepped surfaces by patterning the alternating stack;
forming a retro-stepped dielectric material portion over the stepped surfaces of the alternating stack;
forming a via cavity through the retro-stepped dielectric material portion and the alternating stack;
isotropically expanding the via cavity by laterally recessing the retro-stepped dielectric material portion and the insulating layers selective to the sacrificial material layers to form a finned via cavity;
conformally depositing a dielectric material at peripheral portions of the finned via cavity; and
anisotropically etching the dielectric material to form the stepped via cavity, wherein a remaining portion of the dielectric material comprises the dielectric support pillar.
16 . The method of claim 15 , further comprising:
forming a dielectric liner over the dielectric support pillar; and
forming the sacrificial via fill material portion over the dielectric support pillar.
17 . A method of forming a semiconductor structure, comprising:
forming an alternating stack of insulating layers and sacrificial material layers;
forming memory stack structures through the alternating stack, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements formed at levels of the sacrificial material layers;
forming stepped surfaces by patterning the alternating stack;
forming insulating spacers on vertically-extending surface segments of the stepped surfaces;
forming an etch stop layer over the insulating spacers and horizontal surface segments of the stepped surfaces;
forming a retro-stepped dielectric material portion over the etch stop layer;
forming a via cavity through the retro-stepped dielectric material portion, the etch stop layer, and the alternating stack;
isotropically expanding the via cavity by laterally recessing the retro-stepped dielectric material portion and the insulating layers selective to the sacrificial material layers to form a finned via cavity;
conformally depositing a dielectric material at peripheral portions of the finned via cavity;
anisotropically etching the dielectric material to form a stepped via cavity, wherein a remaining portion of the dielectric material comprises a finned dielectric support pillar;
replacing the sacrificial material layers with electrically conductive layers; and
forming a conductive layer contact via structure that contacts a top surface of a first electrically conductive layer of the electrically conductive layers.
18 . The method of claim 17 , further comprising:
forming a sacrificial via fill material portion on a top surface of the finned dielectric support pillar prior to the replacing the sacrificial material layers with electrically conductive layers;
removing the sacrificial via fill material portion after the replacing the sacrificial material layers with electrically conductive layers;
anisotropically etching a portion of the finned dielectric support pillar after the removing the sacrificial via fill material portion to expose the top surface of the first electrically conductive layer, wherein the conductive layer contact via structure is formed on the annular top surface of the first electrically conductive layer.
19 . The method of claim 17 , wherein:
the finned dielectric support pillar partially fills a lower portion of the stepped via cavity; and
a lower portion of the conductive layer contact via structure is located in the lower portion of the stepped via cavity and is surrounded by the finned dielectric support pillar.
20 . The method of claim 17 , wherein:
the finned dielectric support pillar completely fills a lower portion of the stepped via cavity; and
the conductive layer contact via structure is located on the finned dielectric support pillar.