Three-dimensional memory device with via structures surrounded by perforated dielectric moat structure and methods of making the same
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure vertically extending through the alternating stack, and an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers. The perforated dielectric moat structure includes a plurality of lateral openings at each level of the insulating layers, and does not include any opening at levels of the electrically conductive layers. An interconnection via structure can be laterally surrounded by the perforated dielectric moat structure, and can vertically extend through each insulating layer within the alternating stack.
1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers;
a perforated dielectric moat structure vertically extending through the alternating stack as a single continuous dielectric structure containing a dielectric fill material therein and including a plurality of lateral openings at each level of the insulating layers and not including any opening at levels of the electrically conductive layers, wherein each of the plurality of lateral openings laterally extends through the single continuous structure between an outer sidewall of the perforated dielectric moat structure and an inner sidewall of the perforated dielectric moat structure to define a respective set of volumes in which the dielectric fill material of the single continuous dielectric structure is not present; and
an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack and contacting a top surface of an underlying metal interconnect structure;
wherein: the perforated dielectric moat structure comprises a row of dielectric pillar portions in direct contact with sidewall segments of a respective one of the insulating layers at each level of the insulating layers; and
each of the insulating layers laterally extends between neighboring pairs of dielectric pillar portions from outside an area defined by outer sidewalls of the perforated dielectric moat structure in a plan view along a direction perpendicular to a top surface of the substrate to inside an area defined by the inner sidewalls of the perforated dielectric moat structure in the plan view.
2. The three-dimensional memory device of claim 1 , wherein:
the perforated dielectric moat structure is a continuous unitary structure having a dielectric material composition; and
the interconnection via structure contacts sidewalls of a vertical stack of dielectric material fins having the dielectric material composition and laterally spaced from the perforated dielectric moat structure.
3. The three-dimensional memory device of claim 2 , wherein:
the perforated dielectric moat structure laterally surrounds a dielectric material plate at each level of the electrically conductive layers; and
each dielectric material fin within the vertical stack of dielectric material fins contacts and is laterally surrounded by a respective one of the dielectric material plates.
4. The three-dimensional memory device of claim 3 , wherein:
each dielectric material fin within the vertical stack of dielectric material fins has a same height as the respective one of the dielectric material plates; and
each dielectric material fin within the vertical stack of dielectric material fins has at least one convex cylindrical or cylindrical sector surface that contacts at least one concave cylindrical surface of the respective one of the dielectric material plates.
5. The three-dimensional memory device of claim 3 , wherein:
the perforated dielectric moat structure comprises undoped silicate glass or a doped silicate glass; and
the dielectric material plates comprise silicon nitride.
6. The three-dimensional memory device of claim 4 , wherein each dielectric material fin within the vertical stack of dielectric material fins has a single convex cylindrical surface that contacts an entirety of a single concave cylindrical surface of the respective one of the dielectric material plates.
7. The three-dimensional memory device of claim 4 , wherein:
each dielectric material fin within the vertical stack of dielectric material fins has multiple convex cylindrical sector surfaces that are adjoined to each other at vertically extending edges; and
the multiple convex cylindrical surfaces contact multiple concave cylindrical surfaces of the respective one of the dielectric material plates.
8. The three-dimensional memory device of claim 2 , wherein the dielectric material fins have an areal overlap with each other in a plan view along a vertical direction, and are vertically interconnected to each other through at least one dielectric core pillar that vertically extends through each layer within the alternating stack.
9. The three-dimensional memory device of claim 8 , wherein:
each of the at least one dielectric core pillar contacts a segment of a sidewall of the interconnection via structure; and
each of the insulating layers contacts a respective segment of the sidewall of the interconnection via structure.
10. The three-dimensional memory device of claim 8 , wherein the dielectric material fins are vertically interconnected to each other through a plurality of dielectric core pillars that vertically extend through each layer within the alternating stack.
11. The three-dimensional memory device of claim 1 , wherein each row of dielectric pillar portions is arranged along a periphery of the perforated dielectric moat structure at a level of one of the insulating layers.
12. The three-dimensional memory device of claim 1 , wherein the rows of dielectric pillar portions located at different levels of the insulating layers have an area overlap between them.
13. The three-dimensional memory device of claim 1 , wherein the perforated dielectric moat structure comprises an annular dielectric plate portion at each level of the electrically conductive layers that laterally surrounds a respective dielectric material plate.
14. The three-dimensional memory device of claim 1 , wherein each of the insulating layers laterally extends continuously from outside the perforated dielectric moat structure to inside the perforated dielectric moat structure through the plurality of lateral openings in the perforated dielectric moat structure.
15. The three-dimensional memory device of claim 1 , wherein:
the perforated dielectric moat structure comprises a dielectric moat trench fill material portion composed of undoped silicate glass or a doped silicate glass; and
the perforated dielectric moat structure comprises a blocking dielectric layer laterally surrounding the dielectric moat trench fill material portion.
16. The three-dimensional memory device of claim 15 , wherein:
each of the memory stack structures comprises a respective memory film; and
each memory film comprises a respective vertical stack of memory elements and a respective additional blocking dielectric layer having a same material composition and a same thickness as the blocking dielectric layer within the perforated dielectric moat structure.
17. The three-dimensional memory device of claim 1 , further comprising:
semiconductor devices located on a substrate semiconductor layer; and
lower-level metal interconnect structures embedded in lower-level dielectric material layers and electrically connected to a respective node of the semiconductor devices,
wherein the alternating stack is located above the lower-level metal interconnect structure.
18. The three-dimensional memory device of claim 17 , wherein the interconnection via structure contacts a top surface of one of the lower-level metal interconnect structures.
19. The three-dimensional memory device of claim 18 , further comprising a source-level material layers comprising a doped semiconductor material located between the lower-level dielectric material layers and the alternating stack, wherein the source-level material layers comprises an opening therethrough, and the interconnection via structure vertically extends through the opening in the source-level material layers and contacts a dielectric material portion located within the opening in the source-level material layers.