IP Library › Granted Patent US 12,408,335
Granted Patent B2
US 12,408,335 · App. 17/663,951 · Granted Sep 2, 2025

Three-dimensional memory device containing word line contacts which extend through drain-select-level isolation structures and methods of making the same

Inventors: Michiaki Sano (Yokkaichi, JP); Koichi Ito (Yokkaichi, JP); Takuya Mori (Yokkaichi, JP)
Assignee: Sandisk Technologies, Inc.
H10B41/27H01L23/5226H01L23/5283H10B41/10H10B41/35H10B43/10H10B43/27H10B43/35
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Quick Facts
Patent No.
US 12,408,335
App. No.
17/663,951
Granted
Sep 2, 2025
Kind
B2
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers include word lines and drain select gate electrodes that contain plurality of drain-select-level electrically conductive strips which are located above the word lines, memory stack structures vertically extending through the alternating stack, drain-select-level isolation structures located between a respective neighboring pair of drain-select-level electrically conductive strips, and a first laterally-insulated contact via assembly including a first layer contact via structure and a first tubular insulating spacer. The first laterally-insulated contact via assembly contacts a top surface of a first word line of the word lines, and the first laterally-insulated contact via assembly laterally contacts a first drain-select-level isolation structure of the drain-select-level isolation structures.

Claims (34)

1. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers, wherein the electrically conductive layers comprise word lines and drain select gate electrodes that comprise plurality of drain-select-level electrically conductive strips which are located above the word lines memory stack structures vertically extending through the alternating stack;

drain-select-level isolation structures located between a respective neighboring pair of drain-select-level electrically conductive strips; and

a first laterally-insulated contact via assembly comprising a first layer contact via structure and a first tubular insulating spacer,

wherein:

the first laterally-insulated contact via assembly contacts a top surface of a first word line of the word lines;

the first laterally-insulated contact via assembly laterally contacts a first drain-select-level isolation structure of the drain-select-level isolation structures; and

the first drain-select-level isolation structure laterally extends through the entirety of the first laterally-insulated contact via assembly, and is in direct contact with two planar vertical sidewall segments of the first tubular insulating spacer and with two planar vertical sidewall segments of the first layer contact via structure.

2. The three-dimensional memory device of claim 1 , wherein:

the memory stack structures are arranged in rows of memory stack structures that extend along a first horizontal direction; and

each row of memory stack structures is located between a respective neighboring pair of drain-select-level isolation structures, or between a backside trench fill structure and one of the drain-select-level isolation structures.

3. The three-dimensional memory device of claim 1 , wherein:

the memory stack structures are located within a memory array region; and

the first laterally-insulated contact via assembly is located in a contact region that is laterally offset from the memory array region.

4. The three-dimensional memory device of claim 3 , wherein:

the drain-select-level electrically conductive strips laterally extend along a first horizontal direction and are laterally spaced from each other along a second horizontal direction in the memory array region;

the drain-select-level isolation structures laterally extend along the first horizontal direction in the memory array region; and

the alternating stack is laterally bounded by a first backside trench fill structure and a second backside trench fill structure which extend along the first horizontal direction in the memory array region and the contact region.

5. The three-dimensional memory device of claim 4 , wherein:

the first laterally-insulated contact via assembly comprises a first sidewall segment that is more proximal to a first vertical plane that contains an interface between the alternating stack and the first backside trench fill structure than the first drain-select-level isolation structure is to the first vertical plane, and a second sidewall segment that is more proximal to a second vertical plane that contains an interface between the alternating stack and the second backside trench fill structure than the first drain-select-level isolation structure is to the second vertical plane;

the first vertical plane and the second vertical plane are parallel to the first horizontal direction; and

the first backside trench fill structure and the second backside trench fill structure have greater lateral extents along the first horizontal direction than the first drain-select-level isolation structure.

6. The three-dimensional memory device of claim 3 , wherein:

the contact region is free of any memory stack structures;

support pillar structures comprising a dielectric material and extending through at least a bottommost insulating layer within the alternating stack are located within the contact region;

the first laterally-insulated contact via assembly contacts a top surface of each support pillar structure within a first subset of the support pillar structures; and

each support pillar structure within the first subset of the support pillar structures vertically extends through the first word line and through each layer within the alternating stack that underlies the first word line.

7. The three-dimensional memory device of claim 3 , further comprising drain-select-level contact via structures vertically extending through a topmost insulating layer of the insulating layers of the alternating stack and contacting a top surface of a respective drain-select-level electrically conductive strip of the plurality of drain-select-level electrically conductive strips.

8. The three-dimensional memory device of claim 4 , further comprising an additional drain-select-level isolation structure that is laterally spaced from the first drain-select-level isolation structure and contacts the first tubular insulating spacer, wherein the additional drain-select-level isolation structure is laterally offset from the first drain-select-level isolation structure along the second horizontal direction.

9. The three-dimensional memory device of claim 3 , wherein the word lines in the contact region do not form a stepped staircase.

10. The three-dimensional memory device of claim 1 , further comprising a contact-level dielectric layer overlying the alternating stack, wherein:

an entirety of an annular top surface of the first tubular insulating spacer is located within a horizontal plane including an interface between the alternating stack and the contact-level dielectric layer;

the first layer contact via structure comprises an electrically conductive material that vertically extends through each layer of the alternating stack that overlies the first word line and through the contact-level dielectric layer; and

the first layer contact via structure comprises a first vertical sidewall vertically extending through each layer of the alternating stack that overlies the first word line, a second vertical sidewall vertically extending through the contact-level dielectric layer, and a horizontal surface connecting a top periphery of the first vertical sidewall and a bottom periphery of the second vertical sidewall and located within the horizontal plane.

Assignments (4)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2022
From: SANO, MICHIAKI; ITO, KOICHI; MORI, TAKUYA
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 059948/0521 →
Continuity (1)
Related Publication 20230380151A1 · Nov 23, 2023
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