IP Library › Granted Patent US 12,751,011
Granted Patent B2
US 12,751,011 · App. 18/360,541 · Granted Sep 29, 2026

Three-dimensional memory device containing composite dielectric isolation structure in a staircase region and methods of forming the same

Inventors: Jixin Yu (Milpitas, CA); Koichi Matsuno (Fremont, CA); Ruogu Matthew Zhu (San Jose, CA); Johann Alsmeier (San Jose, CA)
Assignee: Sandisk Technologies, Inc.
H10B43/27H10B41/27
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Quick Facts
Patent No.
US 12,751,011
App. No.
18/360,541
Granted
Sep 29, 2026
Kind
B2
Abstract

A three-dimensional memory device includes laterally spaced apart vertical stacks of electrically conductive layers and insulating layers. A composite dielectric isolation structure provides electrical isolation between neighboring pairs of vertical stacks. The composite dielectric isolation structure includes at least one retro-stepped dielectric material portion, and may further include at least one finned insulating support structure or a vertical stack of dielectric material plates.

Claims (28)

1 . A three-dimensional memory device, comprising:

insulating layers that are vertically spaced apart from each other and that continuously laterally extend between a first first-type lateral isolation trench fill structure and a second first-type lateral isolation trench fill structure that laterally extend along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction;

first electrically conductive layers vertically interlaced with the insulating layers and contacting the first first-type lateral isolation trench fill structure;

second electrically conductive layers vertically interlaced with the insulating layers and contact the second first-type lateral isolation trench fill structure; and

a composite dielectric isolation structure located between the first electrically conductive layers and the second electrically conductive layers and comprising a retro-stepped dielectric material portion, a vertical stack of dielectric material plates, and a pair of second-type lateral isolation trench fill structures that are laterally spaced apart along the first horizontal direction;

wherein each of the second-type lateral isolation trench fill structures comprises a respective insulating liner comprising a respective portion of an insulating liner material and contacting inner sidewalls of the respective etch stop liner, the first insulating layers, the second insulating layers, the first electrically conductive layers, and the second electrically conductive layers.

2 . The three-dimensional memory device of claim 1 , wherein:

the retro-stepped dielectric material portion has a first lateral extent along the second horizontal direction; and

each dielectric material plate in the vertical stack of dielectric material plates has a second lateral extent along the second horizontal direction that is less than the first lateral extent.

3 . The three-dimensional memory device of claim 1 , wherein the dielectric material plates within the vertical stack of dielectric material plates have lateral extents along the first horizontal direction that decrease with a vertical distance from a horizontal plane including a bottommost surface of the vertical stack.

4 . The three-dimensional memory device of claim 1 , wherein each dielectric material plate within the vertical stack of dielectric material plates has a respective sidewall that is parallel to the second horizontal direction and contacts a respective vertical sidewall segment of the retro-stepped dielectric material portion.

5 . The three-dimensional memory device of claim 1 , wherein each dielectric material plate within the vertical stack of dielectric material plates comprises a concave sidewall segment located at a same level as a respective electrically conductive layer selected from the first electrically conductive layers and the second electrically conductive layers, and is in contact with a convex sidewall segment of a structural element selected from the respective electrically conductive layer or a backside blocking dielectric layer that contacts the respective electrically conductive layer.

6 . The three-dimensional memory device of claim 5 , wherein each dielectric material plate within the vertical stack of dielectric material plates further comprises:

a first planar sidewall segment in contact with a planar sidewall segment of a first etch stop liner that contacts a second-type lateral isolation trench fill structure of the pair of second-type lateral isolation trench fill structures; and

a second planar sidewall segment in contact with a planar sidewall segment of the structural element.

7 . The three-dimensional memory device of claim 1 , wherein each of the first-type lateral isolation trench fill structures comprises a respective additional insulating liner comprising a respective additional portion of the insulating liner material.

8 . The three-dimensional memory device of claim 1 , wherein the retro-stepped dielectric material portion has a first variable lateral extent along the first horizontal direction that increases stepwise with a vertical distance from a horizontal plane including a bottommost surface of the vertical stack.

9 . The three-dimensional memory device of claim 8 , wherein the retro-stepped dielectric material portion has a second variable lateral extent along the second horizontal direction that increases gradually without any step along the second horizontal direction.

10 . The three-dimensional memory device of claim 1 , wherein a dielectric material plate within the vertical stack of dielectric material plates comprises:

first sidewall segments laterally extending along the first horizontal direction and contacting one of the second-type lateral isolation trench fill structures;

a second sidewall segment laterally extending along the second horizontal direction and contacting the one of the second-type lateral isolation trench fill structures;

a first concave surface segment located at a level of one of the first electrically conductive layers and in contact with a convex sidewall of a first structural element that is selected from the one of the first electrically conductive layers and a first blocking dielectric layer that contacts the one of the first electrically conducive layers; and

a third sidewall segment laterally extending along the first horizontal direction and in contact with a planar sidewall of the first structural element.

11 . The three-dimensional memory device of claim 1 , wherein a plurality of dielectric material plates within the vertical stack of dielectric material plates has a uniform width along the second horizontal direction that is less than a minimum lateral dimension of the retro-stepped dielectric material portion along the second horizontal direction.

12 . The three-dimensional memory device of claim 1 , further comprising

first memory openings extending through a first alternating stack of the first electrically conductive layers vertically interlaced with the insulating layers;

second memory openings extending through a second alternating stack of the second electrically conductive layers vertically interlaced with the insulating layers; and

memory opening fill structures located in the first and the second memory openings, wherein each of the memory opening fill structures comprises a memory film and a vertical semiconductor channel.

Assignments (4)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2023
From: YU, JIXIN; MATSUNO, KOICHI; ZHU, RUOGU MATTHEW; ALSMEIER, JOHANN
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 065161/0229 →
Continuity (2)
Provisional Application 63492566 · Mar 28, 2023
Related Publication 20240334695A1 · Oct 3, 2024
References Cited (77)
US 9806093B2 · Toyama et al. · 2017 [cited by applicant]
US 9818693B2 · Toyama et al. · 2017 [cited by applicant]
US 9818759B2 · Kai et al. · 2017 [cited by applicant]
US 9853038B1 · Cui et al. · 2017 [cited by applicant]
US 10038006B2 · Furihata et al. · 2018 [cited by applicant]
US 10115681B1 · Ariyoshi · 2018 [cited by applicant]
US 10249640B2 · Yu et al. · 2019 [cited by applicant]
US 10381371B2 · Ogawa et al. · 2019 [cited by applicant]
US 10840260B2 · Kai et al. · 2020 [cited by applicant]
US 10872857B1 · Otsu et al. · 2020 [cited by applicant]
US 10879264B1 · Otsu et al. · 2020 [cited by applicant]
US 10903237B1 · Hosoda et al. · 2021 [cited by applicant]
US 11081443B1 · Mizutani et al. · 2021 [cited by applicant]
US 11114459B2 · Iwai et al. · 2021 [cited by applicant]
US 11133252B2 · Ito et al. · 2021 [cited by applicant]
US 11282783B2 · Otsu et al. · 2022 [cited by applicant]
US 11322440B2 · Kubo · 2022 [cited by applicant]
US 11342245B2 · Cui et al. · 2022 [cited by applicant]
US 11355506B2 · Tokita et al. · 2022 [cited by applicant]
US 11450685B2 · Yoshida · 2022 [cited by applicant]
US 11532570B2 · Mizuno et al. · 2022 [cited by applicant]
US 20190057974A1 · Lu et al. · 2019 [cited by applicant]
US 20210057336A1 · Shao et al. · 2021 [cited by applicant]
US 20210134827A1 · Iwai et al. · 2021 [cited by applicant]
US 20210210424A1 · Otsu et al. · 2021 [cited by applicant]
US 20210210428A1 · Ohsawa et al. · 2021 [cited by applicant]
US 20210210503A1 · Matsuno et al. · 2021 [cited by applicant]
US 20210210504A1 · Otsu et al. · 2021 [cited by applicant]
US 20210242128A1 · Ito et al. · 2021 [cited by applicant]
US 20210366808A1 · Cui et al. · 2021 [cited by applicant]
US 20210366920A1 · Tokita et al. · 2021 [cited by applicant]
US 20210366924A1 · Tokita et al. · 2021 [cited by applicant]
US 20210375918A1 · Zhang · 2021 [cited by applicant]
US 20210384206A1 · Iwai · 2021 [cited by examiner]
US 20210391345A1 · Otsu et al. · 2021 [cited by applicant]
US 20220102273A1 · Kubo · 2022 [cited by applicant]
US 20220102375A1 · Kubo · 2022 [cited by applicant]
US 20220189872A1 · Sano et al. · 2022 [cited by applicant]
US 20220223614A1 · Takuma et al. · 2022 [cited by applicant]
US 20220254728A1 · Matsuno et al. · 2022 [cited by applicant]
US 20220254733A1 · Mizuno et al. · 2022 [cited by applicant]
US 20220328403A1 · Tobioka · 2022 [cited by examiner]
US 20220328413A1 · Kubo et al. · 2022 [cited by applicant]
US 20220328512A1 · Tanaka et al. · 2022 [cited by applicant]
US 20220352091A1 · Yu et al. · 2022 [cited by applicant]
US 20220352196A1 · Shimomura et al. · 2022 [cited by applicant]
US 20220352197A1 · Matsuno et al. · 2022 [cited by applicant]
US 20220375958A1 · Shimabukuro et al. · 2022 [cited by applicant]
US 20230038557A1 · Ogawa et al. · 2023 [cited by applicant]
US 20230041950A1 · Chibvongodze et al. · 2023 [cited by applicant]
US 20230044232A1 · Kai et al. · 2023 [cited by applicant]
US 20230045001A1 · Ogawa et al. · 2023 [cited by applicant]
US 20230057885A1 · Itou et al. · 2023 [cited by applicant]
US 20230064713A1 · Shimomura · 2023 [cited by applicant]
US 20230069307A1 · Shimomura · 2023 [cited by applicant]
CN 112928117A · 2012 [cited by applicant]
Endoh et al., “Novel Ultra High-Density Memory with a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36. [cited by applicant]
U.S. Appl. No. 17/810,097, filed Jun. 30, 2022, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/810,124, filed Jun. 30, 2022, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 18/062,807, filed Dec. 7, 2022, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 18/221,689, filed Jul. 13, 2023, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 18/221,711, filed Jul. 13, 2023, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 18/350,595, filed Jul. 11, 2023, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 18/352,726, filed Jul. 11, 2023, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 18/352,752, filed Jul. 14, 2023, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 18/353,546, filed Jul. 17, 2023, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 18/353,577, filed Jul. 17, 2023, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 18/354,246, filed Jul. 18, 2023, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 18/354,269, filed Jul. 18, 2023, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 18/355,067, filed Jul. 19, 2023, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 18/356,825, filed Jul. 21, 2023, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 18/358,702, filed Jul. 25, 2023, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 18/358,727, filed Jul. 25, 2023, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 63/383,001, filed Nov. 9, 2022, SanDisk Technologies LLC. [cited by applicant]
Tobioka, A. et al., “Three-Dimensional Memory Device Containing Composite Dielectric Isolation Structure in a Staircase Region and Methods of Forming the Same,” U.S. Appl. No. 18/360,641, filed Jul. 27, 2023. [cited by applicant]
ISR—Notification of Transmittal of The International Search Report and Written Opinion of the International Searching Authority for International Patent Application No. PCT/US2024/012887, mailed Jun. 4, 2024, 12 pages. [cited by applicant]
IPRP-WO—Notification Concerning Transmittal of International Preliminary Report on Patentability and Written Opinion of the International Searching Authority for International Patent Application No. PCT/US2024/012887, m… [cited by applicant]