Device having extended source/drain contact and method
A method includes: forming a stack of semiconductor nanostructures on a semiconductor fin; forming a source/drain opening adjacent the stack; forming a bottom dielectric layer on the semiconductor fin; forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the bottom dielectric layer; forming a dielectric layer on the source/drain region; forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having higher etch selectivity than other portions of the dielectric layer; removing the other portions of the dielectric layer, exposing the void; forming a source/drain contact opening that extends to and connects with the void, the source/drain contact opening exposing sidewalls of the source/drain region; forming a liner layer on exposed surfaces of the source/drain region; and forming a conductive core layer on the liner layer, the conductive core layer being in contact with the liner layer on a top surface, sidewalls and a bottom surface of the source/drain region.
1 . A method, comprising:
forming a stack of semiconductor nanostructures on a semiconductor fin;
forming a source/drain opening adjacent the stack;
forming a bottom dielectric layer on the semiconductor fin;
forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the bottom dielectric layer;
forming a dielectric layer on the source/drain region;
forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having higher etch selectivity than other portions of the dielectric layer;
removing the other portions of the dielectric layer, exposing the void;
forming a source/drain contact opening that extends to and connects with the void, the source/drain contact opening exposing sidewalls of the source/drain region;
forming a liner layer on exposed surfaces of the source/drain region; and
forming a conductive core layer on the liner layer, the conductive core layer being in contact with the liner layer on a top surface, sidewalls and a bottom surface of the source/drain region.
2 . The method of claim 1 , wherein the void has width in a horizontal direction in a range of about 10 nanometers to about 15 nanometers.
3 . The method of claim 1 , wherein the void has height in a vertical direction that is in a range of about 10 nanometers to about half of height of the source/drain region.
4 . The method of claim 1 , wherein the forming a dielectric layer is forming a dielectric nitride layer.
5 . The method of claim 1 , wherein the forming a hardened portion includes forming a top portion on an upper surface of the source/drain region and a bottom portion on the semiconductor fin.
6 . The method of claim 1 , wherein the forming a conductive core layer includes forming the conductive core layer in the void, the conductive core layer including a second void.
7 . A method comprising:
forming a stack of semiconductor nanosheet channels on a semiconductor fin;
forming a source/drain opening adjacent the stack;
forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the semiconductor fin;
forming a dielectric layer on the source/drain region and in the void;
exposing the void by removing portions of the dielectric layer on sidewalls of the source/drain region and in the void;
forming an interlayer dielectric on the source/drain region and the dielectric layer;
forming a source/drain contact opening that extends through the interlayer dielectric and connects with the void, the source/drain contact opening exposing sidewalls of the source/drain region; and
forming a conductive core layer in contact with a top surface and sidewalls of the source/drain region.
8 . The method of claim 7 , wherein the void is present following the forming an interlayer dielectric.
9 . The method of claim 7 , wherein the void extends from below a first height level with a bottom surface of a first semiconductor nanosheet channel of the stack that is nearest the semiconductor fin to a second height that is between a top surface of the first semiconductor nanosheet channel and an upper surface of a second semiconductor nanosheet channel of the stack that is above the first semiconductor nanosheet channel.
10 . The method of claim 7 , wherein the forming a conductive core layer includes partially filling the void.
11 . The method of claim 10 , wherein the conductive core layer is separated from a bottom surface of the source/drain region by an unfilled portion of the void.
12 . The method of claim 10 , wherein a portion of the conductive core layer in contact with the bottom surface of the source/drain region has thickness in a range of about 1 nanometer to about 5 nanometers.
13 . The method of claim 7 , further comprising forming a backside via that is in contact with the conductive core layer.
14 . A method comprising:
forming a stack of semiconductor nanostructures on a semiconductor fin;
forming a source/drain opening adjacent the stack;
forming a bottom dielectric layer on the semiconductor fin;
forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the bottom dielectric layer;
forming a dielectric layer on the source/drain region and in the void;
forming an interlayer dielectric over the source/drain region and the dielectric layer;
forming a source/drain contact opening through the interlayer dielectric and connecting with the void, the source/drain contact opening exposing sidewalls of the source/drain region; and
forming a conductive core layer in the source/drain contact opening, the conductive core layer being in contact with a top surface and sidewalls of the source/drain region and extending into the void.
15 . The method of claim 14 , wherein the void has width in a horizontal direction in a range of about 10 nanometers to about 15 nanometers.
16 . The method of claim 14 , wherein the void has height in a vertical direction that is in a range of about 10 nanometers to about half of height of the source/drain region.
17 . The method of claim 14 , wherein the dielectric layer comprises a nitride material.
18 . The method of claim 14 , wherein the forming the dielectric layer includes forming a top portion on an upper surface of the source/drain region and a bottom portion on the semiconductor fin.
19 . The method of claim 14 , wherein the forming the conductive core layer includes partially filling the void.
20 . The method of claim 19 , wherein the conductive core layer is separated from a bottom surface of the source/drain region by an unfilled portion of the void.