IP Library › Granted Patent US 12,248,869
Granted Patent B2
US 12,248,869 · App. 18/469,910 · Granted Mar 11, 2025

Three dimensional circuit implementing machine trained network

Inventors: Steven L. Teig (Menlo Park, CA); Kenneth Duong (San Jose, CA)
Assignee: Adeia Semiconductor Inc.
G06N3/065G06F11/1423G06F11/2007G06F11/2028G06F11/2041G06F11/2051G06N3/04G06N3/048G06N3/063G06N3/08G06N3/082G06N3/084H01L23/3128H01L25/0657G06F2201/85H01L24/16H01L24/17H01L25/043H01L25/074H01L25/0756H01L25/117H01L2224/16145H01L2224/16225H01L2224/16227H01L2224/17181H01L2225/06503H01L2225/06513H01L2225/06517H01L2225/06524H01L2225/06541H01L2225/06565H01L2225/06582H01L2225/06586H01L2924/16235H03K19/21
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Quick Facts
Patent No.
US 12,248,869
App. No.
18/469,910
Granted
Mar 11, 2025
Kind
B2
Abstract

Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

Claims (28)

1. An integrated circuit (IC) device comprising:

a first IC layer comprising a plurality of first computational units serving as neurons of a first neural layer of a neural network to receive first input and generate first output; and

a second IC layer comprising a plurality of second computational units serving as neurons of a second neural layer of the neural network and interconnected with the first computational units, the second computational units to receive as second input the first output from the first neural layer and to generate second output,

wherein the first IC layer and second IC layer are vertically stacked and bonded to each other.

2. The IC device of claim 1 , wherein the second computational units are interconnected with the first computational units through direct-bonded connections between the first and second IC layers.

3. The IC device of claim 1 , wherein the second computational units are interconnected with the first computational units through a hybrid direct-bonded interface between the first and second IC layers.

4. The IC device of claim 1 , further comprising an output memory electrically connected to the first computational units for storing the first output from the first neural layer.

5. The IC device of claim 4 , wherein the output memory comprises a random access memory.

6. The IC device of claim 5 , wherein the output memory is integrated with the first computational units within the first IC layer.

7. The IC device of claim 5 , wherein the output memory is integrated within the second IC layer.

8. The IC device of claim 4 , further comprising a parameter memory for storing machine-training parameters comprising weights and biases, wherein the parameter memory is a different type of memory from the output memory.

9. The IC device of claim 8 , wherein the parameter memory comprises a sequential access memory.

10. The IC device of claim 9 , wherein the parameter memory comprises a read-only memory.

11. The IC device of claim 8 , wherein the parameter memory is integrated with the first computational units within the first IC layer.

12. The IC device of claim 8 , wherein the parameter memory is integrated within the second IC layer.

13. The IC device of claim 1 , wherein the first computational units of the first IC layer serve as neurons of a third neural layer of the neural network to receive as third input the second output from the second computational units of the second IC layer.

14. The IC device of claim 1 , further comprising a third IC layer comprising a plurality of third computational units serving as neurons of a third layer of the neural network to receive as third input the second output from the second neural layer and to generate third output.

15. An integrated circuit (IC) device comprising:

a first IC layer comprising a plurality of first computational units serving as neurons of a first neural subnetwork comprising one or more layers of a neural network; and

a second IC layer comprising a plurality of second computational units serving as neurons of a second neural subnetwork of the neural network comprising one or more layers different from the one or more layers of the first neural subnetwork,

wherein the first computational units and the second computational units are interconnected with each other such that at least one layer of the second neural subnetwork receives output from at least one layer of the first neural subnetwork as input, and

wherein the first IC layer and second IC layer are vertically stacked and bonded to each other.

16. The IC device of claim 15 , wherein the second computational units are interconnected with the first computational units through direct-bonded connections between the first and second IC layers.

17. The IC device of claim 16 , wherein the second computational units are interconnected with the first computational units through a hybrid direct-bonded interface between the first and second IC layers.

18. The IC device of claim 15 , wherein the second IC layer further comprises one or both of a parameter memory for storing machine-trained parameters for or an output memory for storing output from one or more neural layers of the neural network.

19. The IC device of claim 18 , wherein the second IC layer comprises one but not the other of the parameter memory and the output memory, and wherein the other of the parameter memory and the output memory is integrated with the first computational units within the first IC layer.

20. The IC device of claim 19 , wherein the output memory comprises a random access memory.

21. The IC device of claim 19 , wherein the parameter memory comprises a sequential access memory.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2023
From: TEIG, STEVEN L.; DUONG, KENNETH
To: XCELSIS CORPORATION
Reel/Frame 064989/0929 →
CHANGE OF NAME Recorded Sep 21, 2023
From: XCELSIS CORPORATION
To: ADEIA SEMICONDUCTOR INC.
Reel/Frame 065016/0480 →
Continuity (4)
Continuation 17500374 · Oct 13, 2021
Continuation 15859551 · Dec 31, 2017
Provisional Application 62541064 · Aug 3, 2017
Related Publication 20240152743A1 · May 9, 2024
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