3D semiconductor device and structure with metal layers and a power delivery path
A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, and where the third level is bonded to the second level; a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors; and a plurality of capacitors, where the plurality of capacitors include functioning as a decoupling capacitor to mitigate power supply noise.
1. A 3D semiconductor device, the device comprising:
a first level comprising single crystal first transistors, a first metal layer, and a first isolation layer;
a second level comprising second transistors and a second isolation layer,
wherein said first level is overlaid by said second level;
a third level comprising single crystal third transistors,
wherein said second level is overlaid by said third level,
wherein said third level comprises a third isolation layer, and
wherein said third level is bonded to said second level;
a power delivery path to said second transistors,
wherein at least a portion of said power delivery path is connected to at least one of said first transistors; and
a plurality of capacitors,
wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.
2. The device according to claim 1 , further comprising:
a plurality of vias disposed through said second level,
wherein at least one of said plurality of vias comprises tungsten.
3. The device according to claim 1 ,
wherein at least one of said second transistors comprises hafnium oxide.
4. The device according to claim 1 ,
wherein said second level is bonded to said first level.
5. The device according to claim 1 ,
wherein said second level comprises a plurality of DRAM memory cells.
6. The device according to claim 1 ,
wherein at least one of said second transistors comprises a two-sided gate.
7. The device according to claim 1 ,
wherein said first level comprises at least one digital to analog converter circuit.
8. A 3D semiconductor device, the device comprising:
a first level comprising single crystal first transistors, a first metal layer, and a first isolation layer;
a second level comprising second transistors and a second isolation layer,
wherein said first level is overlaid by said second level;
a third level comprising third transistors;
a fourth level comprising a single crystal layer,
wherein said second level is overlaid by said third level,
wherein said third level is overlaid by said fourth level,
wherein said third level comprises a third isolation layer, and
wherein said third level is bonded to said second level;
a power delivery path to said second transistors,
wherein at least a portion of said power delivery path is connected to at least one of said single crystal first transistors; and
a thermal conductive path from said second transistors to an external surface of said 3D semiconductor device.
9. The device according to claim 8 , further comprising:
a plurality of capacitors,
wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.
10. The device according to claim 8 ,
wherein at least one of said second transistors comprises hafnium oxide.
11. The device according to claim 8 ,
wherein said second level is bonded to said first level.
12. The device according to claim 8 ,
wherein said second level comprises a plurality of DRAM memory cells.
13. The device according to claim 8 ,
wherein at least one of said second transistors comprises a two-sided gate.
14. The device according to claim 8 ,
wherein said first level comprises at least one digital to analog converter circuit.
15. A 3D semiconductor device, the device comprising:
a first level comprising single crystal first transistors, a first metal layer, and a first isolation layer;
a second level comprising second transistors and a second isolation layer,
wherein said first level is overlaid by said second level;
a third level comprising third transistors;
a fourth level comprising a single crystal layer,
wherein said second level is overlaid by said third level,
wherein said third level is overlaid by said fourth level,
wherein said third level comprises a third isolation layer, and
wherein said third level is bonded to said second level;
a power delivery path to said second transistors,
wherein at least a portion of said power delivery path is connected to at least one of said first transistors; and
a global power distribution metal layer comprising a metal thickness twice thicker than said first metal layer.
16. The device according to claim 15 , further comprising:
a plurality of capacitors,
wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.
17. The device according to claim 15 , further comprising:
a thermal conductive path from said second transistors to an external surface of said 3D semiconductor device.
18. The device according to claim 15 ,
wherein said second level is bonded to said first level.
19. The device according to claim 15 ,
wherein said second level comprises a plurality of DRAM memory cells.
20. The device according to claim 15 ,
wherein said first level comprises at least one digital to analog converter circuit.