Thin film semiconductor switching device
Novel semiconductor devices are taught. The novel devices include a thin film transistor (TFT) with an n-type semiconductor layer to form a channel between a source and a drain. The TFT further includes a source-channel interfacial member adjacent to at least the source contact of the device to provide depletion layer control of the operation of the TFT.
1 . A method of making a thin-film transistor, the method comprising:
forming a well in a thin-film structure, wherein the thin-film structure includes a source contact and a drain contact;
forming a layer of n-type semiconductor material over the thin-film structure within the well and outside the well;
forming a layer of dielectric material over the layer of n-type semiconductor material within the well and outside the well;
forming a layer of gate material over the layer of dielectric material within the well and outside the well; and
removing portions of the layer of n-type semiconductor material, the layer of dielectric material, and the layer of gate material that are outside the well;
wherein portions of the layer of n-type semiconductor material, the layer of dielectric material, and the layer of gate material remaining within the well are operable with the source contact and the drain contact as the thin-film transistor.
2 . The method of claim 1 , wherein removing the portions of the layer of n-type semiconductor material, the layer of dielectric material, and the layer of gate material that are outside the well comprises polishing.
3 . The method of claim 1 , wherein removing the portions of the layer of n-type semiconductor material, the layer of dielectric material, and the layer of gate material that are outside the well comprises wet chemical etching.
4 . The method of claim 1 , wherein removing the portions of the layer of n-type semiconductor material, the layer of dielectric material, and the layer of gate material that are outside the well comprises dry chemical etching.
5 . The method of claim 1 , wherein removing the portions of the layer of n-type semiconductor material, the layer of dielectric material, and the layer of gate material that are outside the well comprises atomic layer etching.
6 . The method of claim 1 , further comprising forming a source-channel interfacial member over the source contact before forming the layer of n-type semiconductor material.
7 . The method of claim 6 , wherein forming the source-channel interfacial member comprises oxidizing material of the source contact.
8 . The method of claim 6 , wherein forming the source-channel interfacial member comprises depositing the source-channel interfacial member on the source contact.
9 . The method of claim 6 , wherein the source-channel interfacial member comprises a p-type metal oxide and is operable to deplete the carrier channel in a region of the layer of n-type semiconductor material adjacent the source contact to reduce leakage current when the thin-film transistor is off.
10 . The method of claim 1 , wherein forming the layer of n-type semiconductor material comprises using atomic layer deposition.
11 . The method of claim 1 , wherein the n-type semiconductor material is tin oxide.
12 . The method of claim 1 , wherein the drain contact is positioned vertically with respect to the source contact.
13 . The method of claim 1 , further comprising:
forming a layer of gate tuning material over the layer of dielectric material within the well and outside the well before forming the layer of gate material; and
removing a portion of the layer of gate tuning material that is outside the well.
14 . A thin-film transistor comprising:
a thin-film structure including a source contact and a drain contact;
a layer of n-type semiconductor material formed within a well in the thin-film structure;
a layer of dielectric material formed over the layer of n-type semiconductor material within the well;
a layer of gate material formed over the layer of dielectric material within the well; and
a source-channel interfacial member formed over the source contact;
wherein no portion of the layer of n-type semiconductor material, the layer of dielectric material, and the layer of gate material extends outside the well.
15 . The thin-film transistor of claim 14 , wherein the source-channel interfacial member comprises oxidized material of the source contact.
16 . The thin-film transistor of claim 14 , the source-channel interfacial member comprises material deposited on the source contact.
17 . The thin-film transistor of claim 14 , wherein the source-channel interfacial member comprises a p-type metal oxide and is operable to deplete the carrier channel in a region of the layer of n-type semiconductor material adjacent the source contact to reduce leakage current when the thin-film transistor is off.
18 . The thin-film transistor of claim 14 , wherein the n-type semiconductor material is tin oxide.
19 . The thin-film transistor of claim 14 , wherein the drain contact is positioned vertically with respect to the source contact.
20 . The thin-film transistor of claim 14 , further comprising a layer of gate tuning material formed over the layer of dielectric material within the well.
21 . A stack of thin-film transistors comprising:
two or more thin-film transistors stacked vertically and separated by insulating and/or dielectric material, each of the two or more thin-film transistors including:
a thin-film structure including a source contact and a drain contact;
a layer of n-type semiconductor material formed within a well in the thin-film structure;
a layer of dielectric material formed over the layer of n-type semiconductor material within the well;
a layer of gate material formed over the layer of dielectric material within the well; and
wherein the layer of n-type semiconductor material, the layer of dielectric material, and the layer of gate material are flush with an opening of the well.
22 . The stack of thin-film transistors of claim 21 , wherein each of the two or more thin-film transistors further comprises a source-channel interfacial member formed over the source contact, wherein the source-channel interfacial member includes a p-type metal oxide and is operable to deplete the carrier channel in a region of the layer of n-type semiconductor material adjacent the source contact to reduce leakage current when the thin-film transistor is off.
23 . The stack of thin-film transistors of claim 21 , wherein the n-type semiconductor material is tin oxide.
24 . The stack of thin-film transistors of claim 21 , wherein the drain contact is positioned vertically with respect to the source contact.
25 . A thin-film transistor comprising:
a thin-film structure including a source contact and a drain contact;
a layer of n-type semiconductor material formed within a well in the thin-film structure;
a layer of dielectric material formed over the layer of n-type semiconductor material within the well; and
a layer of gate material formed over the layer of dielectric material within the well;
wherein no portion of the layer of n-type semiconductor material, the layer of dielectric material, and the layer of gate material extends outside the well; and
wherein the drain contact is positioned vertically with respect to the source contact.
26 . A thin-film transistor comprising:
a thin-film structure including a source contact and a drain contact;
a layer of n-type semiconductor material formed within a well in the thin-film structure;
a layer of dielectric material formed over the layer of n-type semiconductor material within the well;
a layer of gate material formed over the layer of dielectric material within the well; and
a layer of gate tuning material formed over the layer of dielectric material within the well;
wherein no portion of the layer of n-type semiconductor material, the layer of dielectric material, and the layer of gate material extends outside the well.