Epitaxial oxide materials, structures, and devices
The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, an integrated circuit includes a field effect transistor (FET) and a waveguide coupled to the FET, wherein the waveguide comprises a signal conductor. The FET can include: a substrate comprising a first oxide material; an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer, the gate layer comprising a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The electrical contacts can include: a source electrical contact coupled to the epitaxial semiconductor layer; a drain electrical contact coupled to the epitaxial semiconductor layer; and a first gate electrical contact coupled to the gate layer.
1. An integrated circuit, comprising:
a field effect transistor (FET), comprising:
a substrate comprising a first oxide material;
an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap;
a gate layer on the epitaxial semiconductor layer, the gate layer comprising a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and
electrical contacts comprising:
a source electrical contact coupled to the epitaxial semiconductor layer;
a drain electrical contact coupled to the epitaxial semiconductor layer; and
a first gate electrical contact coupled to the gate layer; and
a waveguide coupled to the FET, the waveguide comprising a signal conductor.
2. The integrated circuit of claim 1 , wherein the substrate is insulating.
3. The integrated circuit of claim 1 , wherein the substrate comprises sapphire oriented in the A-, M- or R-plane.
4. The integrated circuit of claim 1 , wherein the second oxide material comprises a cubic crystal symmetry, and wherein the first oxide material comprises a monoclinic, corundum, or hexagonal crystal symmetry.
5. The integrated circuit of claim 1 , further comprising an epitaxial buffer layer between the substrate and the epitaxial semiconductor layer, wherein the epitaxial buffer layer comprises a fourth oxide material.
6. The integrated circuit of claim 1 , wherein the second oxide material comprises (Al x1 Ga 1−x1 ) 2 O 3 wherein 0≤x1≤1.
7. The integrated circuit of claim 6 , wherein the third oxide material comprises (Al x2 Ga 1−x2 ) 2 O 3 wherein 0≤x2≤1.
8. The integrated circuit of claim 6 , wherein the second oxide material comprises (Al x2 Ga 1−x2 ) 2 O 3 wherein 0≤x2≤1, and wherein the third oxide material comprises (Al x3 Ga 1−x3 ) 2 O 3 wherein 0≤x3≤1.
9. The integrated circuit of claim 1 , wherein the third oxide material comprises single crystal A x B 1−x O n , wherein 0<x<1, wherein A is Al and/or Ga, wherein B is Mg, Ni, a rare earth, Er, Gd, Ir, Bi, or Li.
10. The integrated circuit of claim 7 , wherein the first oxide material is Al 2 O 3 or Ga 2 O 3 .
11. The integrated circuit of claim 7 , wherein the first oxide material is selected from MgO, MgAl 2 O 4 , and MgGa 2 O 4 .
12. The integrated circuit of claim 7 , wherein the first oxide material is LiF or MgF 2 .
13. The integrated circuit of claim 7 , wherein the first oxide material is LiGaO 2 or LiAlO 2 .
14. The integrated circuit of claim 7 , wherein the first oxide material is LaAlO 3 .
15. The integrated circuit of claim 7 , wherein the first oxide material is TiO 2 or quartz.
16. The integrated circuit of claim 1 , wherein the second oxide material comprises (Ni x1 Mg 1−x1 ) y Ga 2(1−y) O 3−2y where 0≤x1≤1 and 0≤y≤1.
17. The integrated circuit of claim 1 , wherein the second oxide material comprises (Gd x1 Ga 1−x1 ) 2 O 3 , (Gd x1 Ga y Al 1−x1−y ) 2 O 3 , or (Gd x1 Al 1−x1 ) 2 O 3 , where 0≤x1≤1, 0≤y≤1.
18. The integrated circuit of claim 1 , wherein the second oxide material comprises (Ir x1 Ga 1−x1 ) 2 O 3 , (Ir x1 Al 1−x1 ) 2 O 3 , (Bi x1 Ga 1−x1 ) 2 O 3 , or (Bi x1 Al 1−x1 ) 2 O 3 , where 0≤x1≤1.
19. The integrated circuit of claim 1 , wherein the second oxide material comprises LiGaO 2 , LiAlO 2 , Li(Al xa Ga 1−xa )O 2 , Li 2xa Ga 2(1−xa) O 3−2xa , or Li 2xa Al 2(1−xa) O 3−2xa , where 0≤xa≤1.
20. The integrated circuit of claim 1 , wherein the gate layer is an epitaxial gate layer.
21. The integrated circuit of claim 1 , wherein the third oxide material is substantially amorphous.
22. The integrated circuit of claim 1 , further comprising a second gate electrical contact coupled to the gate layer, wherein the first gate electrical contact and the second gate electrical contact are offset spatially along a length of a channel of the FET.
23. The integrated circuit of claim 1 , wherein the epitaxial semiconductor layer comprises a fully depleted channel.
24. The integrated circuit of claim 1 , wherein the FET is an RF switch.
25. The integrated circuit of claim 1 , further comprising a phased array antenna coupled to the waveguide.
26. The integrated circuit of claim 1 , further comprising an electric field shield comprising a metal, wherein the electric field shield is positioned above the first gate electrical contact.
27. The integrated circuit of claim 1 , wherein the signal conductor comprises a single stripline signal conductor, or a dual coplanar stripline signal conductor.