Granted Patent B2

US 12,219,769 · App. 18/738,721 · Granted Feb 4, 2025

Inventors: Zvi Or-Bach (Haifa, IL); Jin-Woo Han (San Jose, CA)

Assignee: Monolithic 3D Inc.

H10B43/27H01L23/5283H01L27/0207H01L29/167H01L29/47H01L29/7827H01L29/792H10B43/10H10B43/20H10B41/10H10B41/20H10B53/20

Abstract

Claims (84)

1. A 3D semiconductor device, the device comprising:

a first level comprising a first single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors;

a first metal layer overlaying said first single crystal layer;

a second metal layer overlaying said first metal layer;

a third metal layer overlaying said second metal layer;

a plurality of second transistors disposed atop said third metal layer;

a plurality of third transistors disposed atop said plurality of second transistors;

a fourth metal layer disposed atop said plurality of third transistors;

a memory array comprising word-lines,

wherein said memory array comprises at least four memory mini arrays,

wherein each of said memory mini arrays comprises at least four rows by four columns of memory cells,

wherein at least one of said plurality of second transistors comprises a metal gate, and

wherein each of said memory cells comprises at least one of said plurality of second transistors or at least one of said plurality of third transistors; and

a connection path from said fourth metal to said third metal,

wherein said connection path comprises a via disposed through said memory array, and

wherein said memory control circuit comprises at least one cache memory unit.

2. The 3D semiconductor device according to claim 1 ,

wherein said memory control circuit is configured to control each of said four memory mini arrays independently.

3. The 3D semiconductor device according to claim 1 ,

wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, being processed following a same lithography step.

4. The 3D semiconductor device according to claim 1 ,

wherein said memory control circuit comprises at least one Look Up Table circuit (“LUT”).

5. The 3D semiconductor device according to claim 1 ,

wherein said memory control circuit comprises at least one digital to analog converter circuit for each of said at least four memory mini arrays.

6. The 3D semiconductor device according to claim 1 , further comprising:

an upper level disposed atop said fourth metal layer,

wherein said upper level comprises a mono-crystalline silicon layer.

7. The 3D semiconductor device according to claim 1 ,

wherein said memory control circuit comprises at least one power down control circuit.

8. A 3D semiconductor device, the device comprising:

a first level comprising a single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors;

a first metal layer overlaying said first single crystal layer;

a second metal layer overlaying said first metal layer;

a third metal layer overlaying said second metal layer;

a plurality of second transistors disposed atop said third metal layer;

a plurality of third transistors disposed atop said plurality of second transistors;

a fourth metal layer disposed atop said plurality of third transistors; and

a memory array comprising word-lines,

wherein said memory array comprises at least four memory mini arrays,

wherein each of said at least four memory mini arrays comprises at least four rows by at least four columns of memory cells,

wherein at least one of said plurality of second transistors comprises a metal gate,

wherein at least one of said plurality of second transistors comprises a structure deposited using Atomic Level Deposition (“ALD”),

wherein each of said memory cells comprises at least one of said plurality of second transistors or at least one of said plurality of third transistors, and

wherein said memory control circuit comprises at least one logic counter circuit.

9. The 3D semiconductor device according to claim 8 ,

wherein said memory control circuit is configured such that it is able to control each of said at least four memory mini arrays independently.

10. The 3D semiconductor device according to claim 8 ,

wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, being processed following a same lithography step.

11. The 3D semiconductor device according to claim 8 ,

wherein said first level comprises at least one in-out interface control circuit.

12. The 3D semiconductor device according to claim 8 ,

wherein said first level comprises at least one differential read circuit.

13. The 3D semiconductor device according to claim 8 , further comprising:

an upper level disposed atop said fourth metal layer,

wherein said upper level comprises a mono-crystalline silicon layer.

14. The 3D semiconductor device according to claim 8 , further comprising:

a connection path between said fourth metal and said third metal,

wherein said connection path comprises a via through said memory array.

15. A 3D semiconductor device, the device comprising:

a first level comprising a single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors;

a first metal layer overlaying said first single crystal layer;

a second metal layer overlaying said first metal layer;

a third metal layer overlaying said second metal layer;

a plurality of second transistors disposed atop said third metal layer;

a plurality of third transistors disposed atop said plurality of second transistors;

a fourth metal layer disposed atop said plurality of third transistors;

a memory array comprising word-lines; and

an upper level disposed atop said fourth metal layer,

wherein said upper level comprises a mono-crystalline silicon layer,

wherein said memory array comprises at least four memory mini arrays,

wherein each of said at least four memory mini arrays comprises at least four rows by at least four columns of memory cells,

wherein at least one of said plurality of second transistors comprises a metal gate,

wherein each of said memory cells comprises at least one of said plurality of second transistors or at least one of said plurality of third transistors, and

wherein said memory control circuit comprises at least one digital to analog converter circuit.

16. The 3D semiconductor device according to claim 15 ,

wherein said memory control circuit is configured such that it is able to control each of said at least four memory mini arrays independently.

17. The 3D semiconductor device according to claim 15 ,

wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, being processed following a same lithography step.

18. The 3D semiconductor device according to claim 15 ,

wherein said memory control circuit comprises at least one error correcting circuit.

19. The 3D semiconductor device according to claim 15 ,

wherein said memory control circuit comprises at least one cache memory circuit.

20. The 3D semiconductor device according to claim 15 ,

wherein said memory control circuit comprises a memory refresh circuit.

Assignments (1)

Continuity (15)

References Cited (400)