Granted Patent B1

US 12,283,612 · App. 18/430,771 · Granted Apr 22, 2025

Inventor: Shunpei Yamazaki (Setagaya, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H01L29/24H01L29/04H01L29/1033H01L29/0673

Abstract

Claims (29)

1. A transistor comprising:

a crystalline metal oxide; and

a gate, a source, and a drain,

wherein the crystalline metal oxide comprising a first layer and a second layer,

wherein the first layer has a wider bandgap than the second layer,

wherein the first layer and the second layer form a crystal lattice, and

wherein in the case where a temperature increases, the crystalline metal oxide is configured such that a thickness of the second layer in a c-axis direction is decreased.

2. The transistor according to claim 1 ,

wherein the crystalline metal oxide comprises a first metal oxide, a second metal oxide over the first metal oxide, and a third metal oxide over the second metal oxide, and

wherein the first metal oxide, the second metal oxide, and the third metal oxide each comprise the first layer and the second layer.

3. The transistor according to claim 2 ,

wherein the first layer included in the second metal oxide and the second layer included in the second metal oxide are each placed substantially parallel to a formation surface of the second metal oxide.

4. The transistor according to claim 3 ,

wherein in a channel width direction of the transistor, the third metal oxide covers a top surface and a side surface of the second metal oxide,

wherein the gate covers the top surface and the side surface of the second metal oxide, and

wherein in a region where the side surface of the second metal oxide faces the third metal oxide, a c-axis direction of the third metal oxide is different from a c-axis direction of the second metal oxide.

5. The transistor according to claim 2 ,

wherein the first metal oxide, the second metal oxide, and the third metal oxide each comprise the first layer and the second layer, and

wherein the first layer included in the second metal oxide and the second layer included in the second metal oxide are each placed substantially perpendicularly to a formation surface of the second metal oxide.

6. The transistor according to claim 2 ,

wherein a bottom surface of a first region not overlapping with the second metal oxide in the gate is at a lower position than a bottom surface of the second metal oxide, and

wherein a bottom surface of a second region positioned opposite to the first region with the second metal oxide sandwiched therebetween in the gate is at a lower position than the bottom surface of the second metal oxide.

7. The transistor according to claim 2 ,

further comprising a second gate below the first metal oxide to overlap with at least part of a region where the second metal oxide and the gate overlap with each other.

8. The transistor according to claim 2 ,

wherein the first layer comprises an element M (M is one or more selected from Al, Ga, Y, and Sn) and Zn, and

wherein the second layer comprises In.

9. The transistor according to claim 1 ,

wherein one or both of a channel length and a channel width of the transistor comprises a region of less than or equal to 100 nm.

Priority Claims (4)

Continuity (2)

References Cited (102)