Phase-change memory device and method
View Patent ↗A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.
1. A method comprising:
forming a bottom electrode on a conductive feature;
performing a first etching process on the bottom electrode;
forming a phase-change material (PCM) layer on the bottom electrode;
performing a second etching process on the PCM layer;
forming a dielectric layer over the conductive feature, wherein the dielectric layer laterally surrounds the bottom electrode and the PCM layer; and
forming a top electrode on the dielectric layer, wherein the top electrode protrudes into the dielectric layer to physically contact the PCM layer.
2. The method of claim 1 , wherein forming the bottom electrode comprises depositing a barrier layer, wherein sidewalls of the PCM layer are free of the barrier layer.
3. The method of claim 2 , wherein the first etching process recesses the barrier layer.
4. The method of claim 1 , wherein the first etching process is an Atomic Layer Etching (ALE) process.
5. The method of claim 1 , wherein the second etching process comprises a plasma etching process.
6. The method of claim 1 , wherein the PCM layer comprises GeSbTe (GST).
7. The method of claim 1 , wherein a thickness of the PCM layer is less than a thickness of the dielectric layer.
8. The method of claim 1 , wherein a width of the top electrode is greater than a width of the bottom electrode.
9. A method comprising:
forming a first conductive feature in a first dielectric layer;
depositing a second dielectric layer over the first dielectric layer;
forming an opening in the second dielectric layer;
forming a second conductive feature in the opening in the second dielectric layer, wherein the second conductive feature fills the opening, wherein the second conductive feature is electrically connected to the first conductive feature;
recessing the second conductive feature within the opening;
depositing a phase-change material (PCM) layer on the second conductive feature;
recessing the PCM layer; and
forming a third conductive feature on the PCM layer.
10. The method of claim 9 , wherein a top surface of the second conductive feature is below a top surface of the second dielectric layer.
11. The method of claim 9 , wherein the top surface of the second dielectric layer is free of the PCM layer.
12. The method of claim 9 , wherein the third conductive feature extends along a top surface of the second dielectric layer.
13. The method of claim 9 , wherein a total height of the second conductive feature and the PCM layer is smaller than a height of the second dielectric layer.
14. The method of claim 9 , wherein a top surface of the PCM layer and a top surface of the second dielectric layer are level.
15. The method of claim 9 , wherein a thickness of the bottom electrode is less than a thickness of the PCM layer.
16. The method of claim 9 , wherein forming the second conductive feature comprises depositing a barrier layer in the opening and depositing a conductive material on the barrier layer.
17. A method comprising:
depositing a dielectric layer over a conductive feature; and
forming a phase-change random-access memory (PCRAM) cell in the dielectric layer, wherein the forming the PCRAM cell comprises:
forming a first conductive layer on a top surface of the conductive feature;
forming a second conductive layer over the first conductive layer, wherein the second conductive layer protrudes below a top surface of the dielectric layer, wherein the second conductive layer extends over the dielectric layer; and
forming a phase-change material (PCM) layer sandwiched between the first conductive layer and the second conductive layer.
18. The method of claim 17 further comprising removing portions of the PCM layer that extend over the dielectric layer.
19. The method of claim 17 , wherein a width of the PCM layer is the same as a width of the first conductive layer.
20. The method of claim 17 further comprising forming a barrier layer sandwiched between the first conductive layer and the dielectric layer.