Granted Patent B2

US 12,336,236 · App. 18/442,794 · Granted Jun 17, 2025

Inventors: Yu-Lien Huang (Jhubei, TW); Guan-Ren Wang (Hsinchu, TW); Ching-Feng Fu (Taichung, TW)

Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.

H10D62/115H01L21/764H10B10/12H10D30/6219H10D62/151H10D84/017H10D84/0186H10D84/0188H10D84/0193H10D84/038H10D84/853

Abstract

Claims (50)

1. A device comprising:

a first source/drain region;

a second source/drain region;

an inter-layer dielectric over the first source/drain region and the second source/drain region;

a first source/drain contact extending through the inter-layer dielectric, the first source/drain contact connected to the first source/drain region;

a second source/drain contact extending through the inter-layer dielectric, the second source/drain contact connected to the second source/drain region; and

an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature comprising a dielectric liner and a void, the dielectric liner surrounding the void, the dielectric liner having a uniform thickness along a first sidewall of the first source/drain contact and a second sidewall of the second source/drain contact.

2. The device of claim 1 , wherein the isolation feature has a first width at a top of the isolation feature, a second width at a midpoint of the isolation feature, and a third width at a bottom of the isolation feature, the second width being greater than each of the first width and the third width.

3. The device of claim 1 , wherein the isolation feature has a first width at a top of the isolation feature and a second width at a bottom of the isolation feature, the second width being greater than the first width.

4. The device of claim 1 , further comprising:

an isolation region over a substrate; and

a contact etch stop layer over the isolation region, the dielectric liner and the inter-layer dielectric disposed over the contact etch stop layer.

5. The device of claim 4 , wherein the first source/drain region and the second source/drain region each extend through the contact etch stop layer.

6. The device of claim 4 , wherein the contact etch stop layer is over the first source/drain region and the second source/drain region.

7. The device of claim 1 , wherein the void is filled with air or at a vacuum.

8. The device of claim 1 , wherein the first source/drain region is doped with p-type impurities and the second source/drain region is doped with n-type impurities.

9. The device of claim 1 , further comprising:

a gate structure adjacent the first source/drain region and the second source/drain region.

10. A device comprising:

a first source/drain region;

a second source/drain region;

an inter-layer dielectric over the first source/drain region and the second source/drain region, the inter-layer dielectric having a first relative permittivity;

a first source/drain contact extending through the inter-layer dielectric, the first source/drain contact connected to the first source/drain region;

a second source/drain contact extending through the inter-layer dielectric, the second source/drain contact connected to the second source/drain region; and

an isolation feature contacting a first sidewall of the first source/drain contact and a second sidewall of the second source/drain contact, an upper portion of the isolation feature having a lesser width than a lower portion of the isolation feature, the isolation feature having a second relative permittivity, the second relative permittivity being less than the first relative permittivity.

11. The device of claim 10 , wherein the isolation feature comprises an air gap.

12. The device of claim 10 , wherein the isolation feature has a bowed profile shape.

13. The device of claim 10 , wherein the isolation feature has a reentrant profile shape.

14. The device of claim 10 , further comprising:

a power supply voltage node connected to the first source/drain contact; and

a ground voltage node connected to the second source/drain contact.

15. The device of claim 14 , wherein the first source/drain region is doped with p-type impurities and the second source/drain region is doped with n-type impurities.

16. The device of claim 10 , further comprising:

a gate structure adjacent the first source/drain region and the second source/drain region.

17. A device comprising:

a first channel region;

a second channel region;

a gate structure over the first channel region and the second channel region;

a first source/drain region adjacent the gate structure and the first channel region;

a second source/drain region adjacent the gate structure and the second channel region;

a dielectric layer having a horizontal portion between the first source/drain region and the second source/drain region;

an inter-layer dielectric over the dielectric layer, the inter-layer dielectric comprising a different dielectric material than the dielectric layer, a top surface of the inter-layer dielectric being coplanar with a top surface of the gate structure;

a first source/drain contact extending through the inter-layer dielectric, the first source/drain contact connected to the first source/drain region;

a second source/drain contact extending through the inter-layer dielectric, the second source/drain contact connected to the second source/drain region; and

an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature comprising a liner layer and a void, the liner layer surrounding the void, the liner layer contacting the horizontal portion of the dielectric layer.

18. The device of claim 17 , wherein an upper portion of the isolation feature has a lesser width than a lower portion of the isolation feature.

19. The device of claim 17 , wherein the first channel region and the first source/drain region are part of a p-type transistor, and the second channel region and the second source/drain region are part of an n-type transistor.

20. The device of claim 17 , further comprising:

a first semiconductor fin extending above the dielectric layer, the first semiconductor fin comprising the first channel region; and

a second semiconductor fin extending above the dielectric layer, the second semiconductor fin comprising the second channel region.

Continuity (3)

References Cited (38)